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s3c9664/p9664 ( preliminary s pec) product overview 1- 1 1 product overview sam87ri product family samsung's sam88rcri family of 8-bit single-chip cmos microcontrollers offer fast and efficient cpu, a wide range of integrated peripherals, and support otp device. a dual address/data bus architecture and bit- or nibble-configurable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counters with selectable operating modes are included to support real-time operations. s3c9664 microcontroller the s3c9664 microcontroller with usb function can be used in a wide range of general purpose applications. it is especially suitable for joystick, game pad controller or mouse and is available in 20-pin dip, 24 -pin sdip and 20, 24-pin sop. the s3c9664 single-chip 8-bit microcontroller is fabricated using an advanced cmos process. it is built around the powerful sam88rcri cpu core. stop and idle power-down modes were implemented to reduce power consumption. to increase on-chip register space, the size of the internal register file was logically expanded. the s3c9664 has 4 k bytes of program memory on-chip, and 208 bytes of ram including 16 bytes of working register. using the sam88rcri design approach, the following peripherals were integrated with the sam88rcri core: ? two configurable i/o ports (14 i/o pins on 20 pin package, 18 i/o pins on 24pin package) ? analog-to-digital converter with six input channel and 10-bit resolution ? one 8-bit basic timer for watchdog function ? one 8 bit timer/counter with three operating modes (timer 0) ? one 8 bit timer (timer 1) otp the s3c9664 microcontroller is also available in otp (one time programmable) version, S3P9664. S3P9664 microcontroller has an on-chip 4 k byte one-time-programmable eprom instead of masked rom. the S3P9664 is compatible to s3c9664, both in function and in pin configuration.
product overview s3c9664/p9664 ( preliminary s pec) 1- 2 features cpu ? sam88rcri cpu core memory ? 4 -k byte internal program memory ? 208-b yte general purpose register area ? 16 bytes of working register instruction set ? 41 instructions ? idle and stop instructions added for power- down modes instruction execution time ? 0.66 m s at 6 mhz f osc interrupts ? 28 interrupt sources and one vector (24 pins) ? 24 interrupt sources and one vector (20 pin) ? one interrupt level general i/o ? three i/o ports (total 18 i/o pins at 24 sop/sdip) ? three i/o ports (total 14 i/o pins at 20 sop/dip) timer/counter ? one 8-bit basic timer for watchdog function ? one 8 bit timer/counter with three operating modes(match, capture, pwm) ? one 8-bit timer usb ? compatible to usb low speed (1.5 mbps) device 1.1 specification. ? serial bus interface engine (sie) ? packet decoding/generation ? crc generation and checking ? nrzi encoding/decoding and bit-stuffing ? two 8-byte receive/transmit usb buffer a/d converter ? six analog input pins ? 10-bit conversion resolution low voltage reset ? low voltage reset ? power on reset sub oscillator ? internal rc sub oscillator ? auto interrupt wake-up oscillator frequency ? 6 mhz crystal/ceramic oscillator ? external clock source (6 mhz) operating temperature range ? ? 4 0 c to + 85 c operating voltage range ? 4. 0 v to 5.25 v package types ? 24-pin sop/sdip ? 20-pin sop/dip
s3c9664/p9664 ( preliminary s pec) product overview 1- 3 block diagram sam88rcri cpu port i/o and interrupt control 4k rom 208 byte ram test reset notes: 1. 24 sop/sdip 2. 20 sop/dip timer 1 x in x out osc sub osc basic timer timer 0 port 0 usb sie d+/int2 d-/int2 p0.2/int0 p0.3/int0 p0.4/int0 p0.5/int0 p0.0/int0/t0 p0.1/int0 p0.6/int0 p0.7/int0 p1.7/int1 p1.8/int1 p1.2/int1/adc2 p1.3/int1/adc3 p1.4/int1/adc4 p1.5/int1/adc5 p1.0/int1/adc0 p1.1/int1/adc1 port 1/ ad converter figure 1-1. block diagram
product overview s3c9664/p9664 ( preliminary s pec) 1- 4 pin assignments v ss x out x in test p0.0/int0/t0 (cap/pwm) p0.1/int0 reset p0.2/int0 p0.3/int0 p0.4/int0 s3c9664 (20-sop-300) (20-dip-300) 1 2 3 4 5 6 7 8 9 10 v dd d-/p2.0/int2 d+/p2.1/int2 p1.0/ad0/int1 p1.1/ad1/int1 p1.2/ad2/int1 p1.3/ad3/int1 p1.4/ad4/int1 p1.5/ad5/int1 p0.5/int0 20 19 18 17 16 15 14 13 12 11 figure 1-2. pin assignment (20 pin ) v ss x out x in test p0.0/int0/t0 (cap/pwm) p0.1/int0 reset p0.2/int0 p0.3/int0 p0.4/int0 p0.6/int0 p0.7/int0 s3c9664 (24-sop-300) (24-sdip-300) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v dd d-/p2.0/int2 d+/p2.1/int2 p1.0/ad0/int1 p1.1/ad1/int1 p1.2/ad2/int1 p1.3/ad3/int1 p1.4/ad4/int1 p1.5/ad5/int1 p0.5/int0 p1.6/int1 p1.7/int1 figure 1-3. pin assignment (24 pin)
s3c9664/p9664 ( preliminary s pec) product overview 1- 5 table 1- 1 . pin descriptions pin name in/out pin description pin type pin numbers share pins p0.0? p0.7 i/o bit-programmable i/o port for schmitt trigger input , push-pull output and n- ch open drain output. pull-up/ pull-down resistors are assignable by software. port1 pins can also be used as external interrupt. g 5,6,8?11 (5,6,8?12,15) t0, int0 p1.0- p1.5 i/o bit-programmable i/o port for schmitt trigger input, schmitt trigger input with pull-up and n- ch open drain output. port1 pins can also be used as a/d converter channel. f 12?17 (16?21) ad0?5 int1 p1.6- p1.7 i/o bit-programmable i/o port for schmitt trigger input , schmitt trigger input with pull-up and n- ch open drain output and push-pull output. e (13?14) int1 p2.0/d? ? p2.1/d+ i/o bit-programmable i/o port for schmitt trigger input , schmitt trigger input with pull-up and n- ch open drain output and push-pull output. port 2 can be individually configured as external interrupt inputs. also it can be configured as an usb ports e 18?19 (22?23) int2 x in , x out ? crystal/ceramic oscillator signal for system clock. ? 2?3 (2?3) ? reset i system reset signal input pin. b 7 (7) ? test i test signal input pin(for factory use only; muse be connected to v ss ) ? 4 (4) ? v dd ,v ss ? voltage input pin and ground ? 1,20 (1,24) ? t0 i/o timer 0 capture input or pwm output pin g 6 (6) p0.0 int0 i external interrupt input g 5,6,8?11 (5,6,8?12,15) p0.0?p0.7 int1 i external interrupt input f,e 12?17 (13?14, 16?21) p1.0?p1.7 int2 i external interrupt input e 18?19 p2.0?p2.1 ad0? ad5 i a/d converter input f 12?17 (16?21) p1.0?p1.5 note : pin numbers show in parentheses "( )" are for the 24-pin package
product overview s3c9664/p9664 ( preliminary s pec) 1- 6 p-channel n-channel v dd out output disable data figure 1-4. pin circuit type c v dd pull-up enable v dd in/out pne output disable data 47 k figure 1-6. pin circuit type e i/o output disable data circuit type c pull-up enable v dd data figure 1-5. pin circuit type d circuit type c v dd output disable data pull-up enable data to adc in/out 47 k figure 1-7. pin circuit type f
s3c9664/p9664 ( preliminary s pec) product overview 1- 7 v dd v dd in/out pne output disable data pull-up enable 47 k pull-down enable 47 k figure 1-8. pin circuit type g
s3c9664/p9664 (p reliminary s pec ) address spaces 2- 1 2 address spaces overview the s3c9664 microcontroller has two kinds of address space: ? program memory (rom) ? internal register file a 13-bit address bus supports both program memory. special instructions and related internal logic determine when the 13-bit bus carries addresses for program memory. a separate 8 -bit register bus carries addresses and data between the cpu and the internal register file. the s3c9664 has 4 k bytes of mask-programmable program memory on-chip . the s3c9664 microcontroller has 192 bytes general-purpose registers in its internal register file. forty-nine bytes in the register file are mapped for system and peripheral control functions.
address spaces s3c9664/p9664 (p reliminary s pec ) 2- 2 program memory (rom) normal operating mode (internal rom) the s3c9664 has 4 k bytes of internal mask-programmable program memory. the first 2 bytes of the rom (0000h? 0001h) are an interrupt vector address. the program reset address in the rom is 0100h. 4,096 256 1000h 0100h 0 4 k byte internal program memory area interrupt vector 1 2 0002h 0001h program start 0000h s3c9664 figure 2- 1. s3c9664 program memory address space
s3c9664/p9664 (p reliminary s pec ) address spaces 2- 3 register architecture the upper 6 4 bytes (page 0) and the expanded one byte (ffh, page 1) of the s3c9664 's internal register file are addressed as working registers, system cont r ol registe r s and periphe r al control registers. the lower 192 bytes of internal register file (00h? b fh) is called the general purpose register space . for many sam88rcri microcontrollers, the addressable area of the internal register file is further expanded by the additional of one or more register pages at general purpose register space (00h?bfh). this register file expansion is not implemented in the s3c9664 . ffh c0h bfh 00h 192 bytes 64 bytes of common area d0h cfh e0h dfh working registers system control registers peripheral control registers general purpose register file and stack area page 0 page 0 feh (expanded peripheral control register) figure 2- 2 . internal register file organization
address spaces s3c9664/p9664 (p reliminary s pec ) 2- 4 common working register area (c0h?cfh) the sam88rcr i register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. this16-byte address range is called common area. that is, locations in this area can be used as working registers by operations that address any location on any page in the register file. typically, these working registers serve as temporary buffers for data operations between different pages. however, because the s3c9664 uses only page 0, you can use the common area for any internal data operation. the register (r) addressing mode can be used to access this area registers are addressed either as a single 8-bit register or as a paired 16-bit register. in 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. msb rn lsb rn + 1 n = even address figure 2- 3 . 16-bit register pairs + + programming tip ? addressing the common working register area as the following examples show, you should access working registers in the common area, locations c0h?cfh, using working register addressing mode only. example s: 1. ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: ld r2,40h ; r2 (c2h) ? the value in location 40h 2. add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: add r3,#45h ; r3 (c3h) ? r3 + 45h
s3c9664/p9664 (p reliminary s pec ) address spaces 2- 5 system stack s3c9 -series microcontrollers use the system stack for subroutine calls and returns and to store data. the push and pop instructions are used to control system stack operations. the s3c9664 architecture supports stack operations in the internal register file. stack operations return addresses for procedure calls and interrupts and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by the ret instruction. when an interrupt occurs, the contents of the pc and the flags register are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address is always decremented before a push operation and incremented after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2-4 . stack contents after a call instruction stack contents after an interrupt top of stack flags pch pcl pcl pch top of stack low address high address figure 2- 4 . stack operations stack pointer (sp) register location d9h contains the 8-bit stack pointer (sp) that is used for system stack operations. after a reset, the sp value is undetermined. because only internal memory space is implemented in the ks86c6504/p6504 , the sp must be initialized to an 8-bit value in the range 00h? b fh. note in case a stack pointer is initialized to 00h, it is decrea s ed to ffh when stack operation starts. this means that a stack pointer access invalid stack area.
address spaces s3c9664/p9664 (p reliminary s pec ) 2- 6 + + programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operations in the internal register file using push and pop instructions: ld sp,#0c0h ; sp ? c0h (normally, the sp is set to 0c0h by the ; initialization routine) ? ? ? push sym ; stack address 0bfh ? sym push 20h ; stack address 0bdh ? 20h push r3 ; stack address 0bch ? r3 ? ? ? pop r3 ; r3 ? stack address 0bch pop 20h ; 20h ? stack address 0bdh pop sym ; sym ? stack address 0bfh
s3c9664/p9664 (p reliminary s pec ) addressing modes 3- 1 3 addressing modes overview instructions that are stored in program memory are fetched for execution using the program counter. instructions indicate the operation to be performed and the data to be operated on. addressing mode is the method used to determine the location of the data operand. the operands specified in sam88rc r i instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the sam88rcri instruction set supports six explicit addressing modes. not all of these addressing modes are available for each instruction. the addressing modes and their symbols are as follows: ? register (r) ? indirect register (ir) ? indexed (x) ? direct addr ess (da) ? relative address (ra) ? immediate (im)
addressing modes s3c9664/p9664 (p reliminary s pec ) 3- 2 register addressing mode (r) in register addressing mode, the operand is the content of a specified register (see figure 3- 1). working register addressing differs from register a ddressing because it uses a 16- byte working register s pace in the register file and a 4-bit register within that space (see figure 3- 2). dst value used in instruction execution opcode operand 8-bit register file address point to one rigister in register file one-operand instruction (example) sample instruction: dec cntr ; where cntr is the label of an 8-bit register address program memory register file figure 3- 1 . register addressing dst opcode 4-bit working register point to the woking register (1 of 16) two-operand instruction (example) sample instruction: add r1, r2 ; where r1 = c1h and r2 = c2h program memory register file src 4 lsbs operand cfh c0h . . . . figure 3- 2 . working register addressing
s3c9664/p9664 (p reliminary s pec ) addressing modes 3- 3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space (see figures 3- 3 through 3- 6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. 8-bit register file address one-operand instruction (example) dst address of operand used by instruction opcode address point to one rigister in register file sample instruction: rl @shift ; where shift is the label of an 8-bit register address program memory register file value used in instruction execution operand figure 3- 3 . indirect register addressing to register file
addressing modes s3c9664/p9664 (p reliminary s pec ) 3- 4 indirect register addressing mode ( c ontinued ) dst opcode pair points to rigister pair example instruction references program memory sample instructions: call @rr2 jp @rr2 program memory register file value used in instruction operand register program memory 16-bit address points to program memory figure 3- 4 . indirect register addressing to program memory
s3c9664/p9664 (p reliminary s pec ) addressing modes 3- 5 indirect register addressing mode (c ontinued ) dst opcode operand 4-bit working register address point to the woking register (1 of 16) sample instruction: or r6, @r2 program memory register file src 4 lsbs value used in instruction operand cfh c0h . . . . figure 3- 5 . indirect working register addressing to register file
addressing modes s3c9664/p9664 (p reliminary s pec ) 3- 6 indirect register addressing mode (c oncluded ) dst opcode 4-bit working register address sample instructions: lcd r5,@rr6 ; program memory access lde r3,@rr14 ; external data memory access lde @rr4, r8 ; external data memory access program memory register file src value used in instruction operand example instruction references either program memory or data memory program memory or data memory next 3 bits point to working register pair (1 of 8) lsb selects register pair 16-bit address points to program memory or data memory cfh . . . . c0h figure 3- 6 . indirect working register addressing to program or data memory
s3c9664/p9664 (p reliminary s pec ) addressing modes 3- 7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see figure 3- 7). you can use indexed addressing mode to access locations in the internal register file or in external memory. in short offset indexed addressing mode, the 8- bit displacement is treated as a signed integer in the range of ?128 to +127. this applies to external memory accesses only (see figure 3- 8). for register file addressing, an 8-b it base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to the base address (see figure 3- 9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory, external program memory, and for external data memory, when implemented. dst opcode two-operand instruction example point to one of the woking register (1 of 16) sample instruction: ld r0, #base[r1] ; where base is an 8-bit immediate value program memory register file 4 lsbs value used in instruction operand index base address ~ ~ ~ ~ + src figure 3- 7 . indexed addressing to register file
addressing modes s3c9664/p9664 (p reliminary s pec ) 3- 8 indexed addressing mode (c ontinued ) point to working register pair (1 of 8) lsb selects 16-bit address added to offset dst opcode program memory xs (offset) 4-bit working register address sample instructions: ldc r4, #04h[rr2] ; the values in the program address (rr2 + #04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 3 bits register pair src 8-bits 16-bits + program memory or datamemory operand value used in instruction 16-bits register file figure 3- 8 . indexed addressing to program or data memory with short offset
s3c9664/p9664 (p reliminary s pec ) addressing modes 3- 9 indexed addressing mode (c oncluded ) point to working register pair (1 of 8) lsb selects 16-bit address added to offset program memory 4-bit working register address sample instructions: ldc r4, #1000h[rr2] ; the values in the program address (rr2 + #1000h) are loaded into register r4. lde r4, #1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 3 bits register pair 8-bits 16-bits + program memory or datamemory operand value used in instruction 16-bits register file opcode xl h (offset) xl l (offset) dst src figure 3- 9 . indexed addressing to program or data memory with long offset
addressing modes s3c9664/p9664 (p reliminary s pec ) 3- 10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. dst/src opcode program memory "0" or "1" lower address byte lsb selects program memory or data memory: "0" = program memory "1" = data memory memory address used upper address byte program or data memory figure 3- 10 . direct addressing for load instructions
s3c9664/p9664 (p reliminary s pec ) addressing modes 3- 11 direct address mode (c ontinued ) opcode program memory upper address byte program memory address used lower address byte sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address next opcode figure 3- 11 . direct addressing for call and jump instructions
addressing modes s3c9664/p9664 (p reliminary s pec ) 3- 12 relative address mode (ra) in relative address (ra) mode, a two's-complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. the instructions that support ra addressing is jr. opcode program memory displacement program memory address used sample instructions: jr ult,$ + offset ; where offset is a value in the range + 127 to - 128 next opcode + signed displacement value current instruction current pc value figure 3- 12 . relative addressing immediate mode (im) in immediate (im) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. immediate addressing mode is useful for loading constant values into registers. (the operand value is in the instruction) opcode sample instruction: ld r0,#0aah program memory operand figure 3- 13 . immediate addressing
s3c9664/p9664 (p reliminary s pec ) control registers 4- 1 4 control registers overview in this section, detailed descriptions of the s3c9664 control registers are presented in an easy-to-read format. these descriptions will help familiarize you with the mapped locations in the register file. you can also use them as a quick-reference source when writing application programs. system and peripheral registers are summarized in table 4- 1. figure 4- 1 illustrates the important features of the standard register description format. control register descriptions are arranged in alphabetical order according to register mnemonic. more information about control registers is presented in the context of the various peripheral hardware descriptions in part ii of this manual.
control registers s3c9664/p9664 (p reliminary s pec ) 4- 2 table 4- 1. register map and reset status (page 0) register name mnemonic hex r/w general purpose register file & stack area ? 00-bfh r/w working register area ? c0h-cfh r/w timer 0 counter register t0cnt d0h r timer 0 data register t0data d1h r/w timer 0 control register t0con d2h r/w timer 0 interrupt control register t0int d3h r/w clock control register clkcon d4h r/w system flags register flags d5h r/w a/d converter data register (low byte) addatal d6h r a/d converter data register (high byte) addatah d7h r a/d control register adcon d8h r/w stack pointer register sp d9h r/w port 2 data register p2 dah r/w location d bh is not mapped. basic timer control register btcon dch r/w basic timer counter btcnt ddh r location d eh is not mapped. system mode register sym dfh r/w port 0 data register p0 e0h r/w port 1 data register p1 e1h r/w timer 1 counter register t1cnt e2h r timer 1 control register t1con e3h r/w port 0 pull-up/down register (low byte) p0purl e4h r/w port 0 pull-up/down register (high byte) p0purh e5h r/w port 0 control register (low byte) p0conl e6h r/w port 0 control register (high byte) p0conh e7h r/w port 1 control register (low byte) p1conl e8h r/w port 1 control register (high byte) p1conh e9h r/w port 0 interrupt enable register p0int eah r/w port 0 interrupt pending register p0pnd ebh r/w port 1 interrupt enable register p1int ech r/w port 1 interrupt pending register p1pnd edh r/w timer 1 data register t1data eeh r/w port 2 control/interrupt and pending register p2conint efh r/w
s3c9664/p9664 (p reliminary s pec ) control registers 4- 3 table 4- 1. register map and reset status (page 0) (continued) register name mnemonic hex r/w usb function address register faddr f0h r/w usb control endpoint status register ep0csr f1h r/w usb interrupt endpoint 1 status register ep1csr f2h r/w usb control endpoint byte count register ep0bcnt f3h r/w usb control endpoint fifo register ep0fifo f4h r/w usb interrupt endpoint 1 fifo register ep1fifo f5h r/w usb interrupt pending register usbpnd f6h r/w usb interrupt enable register usbint f7h r/w usb power management register pwrmgr f8h r/w usb interrupt endpoint 2 status register ep2csr f9h r/w usb interrupt endpoint 2 fifo register ep2fifo fah r/w endpoint mode register epmode fbh r/w usb interrupt endpoint 1 byte count register ep1bcnt fch r/w usb interrupt endpoint 2 byte count register ep2bcnt fdh r/w usb control register usbcon feh r/w sub control register subcon ffh r/w table 4-2. register map and reset status (page 1) register name mnemonic hex r/w xcon register xcon feh w
control registers s3c9664/p9664 (p reliminary s pec ) 4- 4 flags - system flags register .7 .6 .5 bit identifier reset reset value read/write r = read-only w = write-only r/w = read/write ' - ' = not used bit number: msb = bit 7 lsb = bit 0 addressing mode or modes you can use to modify register values description of the effect of specific bit settings reset value notation: '-' = not used 'x' = undetermind value '0' = logic zero '1' = logic one bit number(s) that is/are appended to the register name for bit addressing d5h register address (hexadecimal) full register name register mnemonic name of individual bit or bit function .7 .6 .5 .4 .2 .3 .1 .0 x r/w x r/w x r/w x r/w 0 r/w x r/w 0 r/w x r/w carry flag (c) 0 operation dose not generate a carry or borrow condition 1 operation generates carry-out or borrow into high-order bit7 zero flag 0 operation result is a non-zero value 1 operation result is zero sign flag 0 operation generates positive number (msb = "0") 1 operation generates negative number (msb = "1") figure 4-1. register description format
s3c9664/p9664 (p reliminary s pec ) control registers 4- 5 adcon ? a/d converter control register page 0, d8h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? 0 0 0 0 0 0 0 read/write ? r/w r/w r/w r/w r/w r/w r/w .7 not used for the s3c9664/p9664 .6?.4 analog input pin selection bits 0 0 0 adc0 (p1.0) 0 0 1 adc1 (p1.1) 0 1 0 adc2 (p1.2) 0 1 1 adc3 (p1.3) 1 0 0 adc4 (p1.4) 1 0 1 adc5 (p1.5) 1 1 0 not used for the s3c9664/p9664 1 1 1 not used for the s3c9664/p9664 .3 end-of-conversion status bit 0 a/d conversion not complete (when read) 1 a/d conversion is complete (when read) .2?.1 conversion speed selection bits 0 0 f osc /16 0 1 f osc /8 1 0 f osc /4 1 1 f osc .0 conversion start bit 0 automatically reset after conversion starting 1 starting note : to configure an a/d converter input channel, you must also make the proper setting in the port 1 control register, p1conl (adc0?adc3) or p1conh (adc4?adc5). only one input can be configured at one time.
control registers s3c9664/p9664 (p reliminary s pec ) 4- 6 btc on ? basic timer co ntrol register page 0, dch bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 ? .4 watchdog timer en able bits 1 0 1 0 disable watchdog function any other value enable watchdog function .3 ? .2 basic timer input clock selection bits 0 0 f osc /4096 0 1 f osc /1024 1 0 f osc /128 1 1 non divided (f osc ) .1 basic timer counter clear bit ( note ) 0 no effect 1 clear btcnt .0 basic timer divider clear bit ( note ) 0 no effect 1 clear both dividers note : when you write a "1" to btcon.0 (or btcon.1), the basic timer counter (or basic timer divider) is cleared. the bit is then cleared automatically to "0".
s3c9664/p9664 (p reliminary s pec ) control registers 4- 7 clkcon ? system clock control register page 0, d4h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 ? ? 0 0 ? ? ? read/write r/w ? ? r/w r/w ? ? ? .7 oscillator irq wake-up function bit 0 enable irq for main system oscillator wake-up in power down mode 1 disable irq for main system oscillator wake-up in power down mode .6 and .5 not used for s3c9664 .4 and .3 cpu clock (system clock) selection bits 0 0 divide by 16 (f osc /16) 0 1 divide by 8 (f osc /8) 1 0 divide by 2 (f osc /2) 1 1 non-divided clock (f osc ) .2 ? .0 not used for s3c9664
control registers s3c9664/p9664 (p reliminary s pec ) 4- 8 ep0bcnt ? endpoint 0 write counter register page 0, f3h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r r r r r/w r r r .7 data toggle check bit 0 data 0 transaction toggle 1 data 1 transaction toggle .6 reserved .5 over 8 bytes received bit 0 normal operation 1 indicates over 8 bytes received .4 enable bit 0 disable endpoint 0 1 enable endpoint 0 .3 ? .0 the byte counter of data stored in endpoint 0 0 0 0 0 minimum bytes stored in endpoint 0 1 0 0 0 maximum bytes stored in endpoint 0
s3c9664/p9664 (p reliminary s pec ) control registers 4- 9 ep1bcnt ? endpoint 1 write counter register page 0, fch bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r r r r r/w r r r .7 data toggle check bit 0 data 0 transaction toggle 1 data 1 transaction toggle .6 reserved .5 over 8 bytes received bit 0 normal operation 1 indicates over 8 bytes received .4 enable bit 0 disable endpoint 1 1 enable endpoint 1 .3 ? .0 the byte counter of data stored in endpoint 1 0 0 0 0 minimum bytes can be stored in endpoint 1 1 0 0 0 maximum bytes can be stored in endpoint 1
control registers s3c9664/p9664 (p reliminary s pec ) 4- 10 ep2bcnt ? endpoint 2 write counter register page 0, fdh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r r r r r/w r r r .7 data toggle check bit 0 data 0 transaction toggle 1 data 1 transaction toggle .6 reserved .5 over 8 bytes received bit 0 normal operation 1 indicates over 8 bytes received .4 enable bit 0 disable endpoint 2 1 enable endpoint 2 .3 ? .0 the byte counter of data stored in endpoint 2 0 0 0 0 minimum bytes can be stored in endpoint 2 1 0 0 0 maximum bytes can be stored in endpoint 2
s3c9664/p9664 (p reliminary s pec ) control registers 4- 11 ep0csr ? control endpoint status register page 0, f 1 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 setup_end clear bit 0 no effect (when write) 1 clear setup_end (bit4) bit .6 out_pkt_rdy clear bit 0 no effect (when write) 1 clear out_pkt_rdy (bit0) bit .5 stall signal sending bit 0 no effect (when write) 1 send stall signal to host .4 setup transfer end bit 0 no effect (when write) 1 sie sets this bit when a control transfer ends before data_end (bit3) is set . 3 setup data end bit 0 no effect (when write) 1 mcu set this bit after loading or unloading the last packet data into the fifo . 2 stall signal receive bit 0 mcu clear this bit to end the stall condition 1 sie sets this bit if a control transaction is ended due to a protocol violation . 1 in packet ready bit 0 sie clear this bit once the packet has been successfully sent to the host 1 mcu sets this bit after writing a packet of data into endpoint0 fifo . 0 out packet ready bit 0 no effect (when write) 1 sie sets this bit once a valid token is written to the fifo
control registers s3c9664/p9664 (p reliminary s pec ) 4- 12 ep1csr ? interrupt endpoint status register page 0, f2 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 1 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w a) the belows are configured as in mode. .7 data_toggle clear bit 0 no effect (when write) 1 clears the data toggle sequence bit .6 ? .3 maximum packet size bits 0 no effect (when write) 1 indicates the maximum packet size for interrupt endpoint .2 fifo flush bit 0 no effect (when write) 1 fifo is flushed, and in_pkt_rdy cleared .1 force stall bit 0 mcu clears this bit to end the stall condition 1 issues a stall handshake to usb .0 in packet ready bit 0 sie clear this bit once the packet has been successfully sent to the host 1 mcu sets this bit after writing a packet of data into endpoint 1 fifo
s3c9664/p9664 (p reliminary s pec ) control registers 4- 13 ep1csr ? interrupt endpoint status register page 0, f2 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w b) the belows are configured as out mode. .7 reserved .6 out_pkt_rdy clear bit 0 no effect (when write) 1 clear out_pkt_rdy (bit0) bit .5-.4 reserved .3 stall signal receive bit 0 mcu can clear this bit 1 sie sets this bit after sending stall packet .2 fifo flush bit 0 no effect (when write) 1 fifo is flushed, and in_pkt_rdy cleared .1 force stall bit 0 mcu clears this bit to end the stall condition 1 issues a stall handshake to usb .0 out packet ready bit 0 no effect (when write) 1 sie sets this bit once a valid data is written to the fifo
control registers s3c9664/p9664 (p reliminary s pec ) 4- 14 ep2csr ? interrupt endpoint status register page 0, f9 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 1 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w a) the belows are configured as in mode. .7 data_toggle clear bit 0 no effect (when write) 1 clears the data toggle sequence bit .6 ? .3 maximum packet size bits 0 no effect (when write) 1 indicates the maximum packet size for interrupt endpoint .2 fifo flush bit 0 no effect (when write) 1 fifo is flushed, and in_pkt_rdy cleared .1 force stall bit 0 mcu clears this bit to end the stall condition 1 issues a stall handshake to usb .0 in packet ready bit 0 sie clear this bit once the packet has been successfully sent to the host 1 mcu sets this bit after writing a packet of data into endpoint 2 fifo
s3c9664/p9664 (p reliminary s pec ) control registers 4- 15 ep2csr ? interrupt endpoint status register page 0, f9 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w b) the belows are configured as out mode. .7 reserved .6 out_pkt_rdy clear bit 0 no effect (when write) 1 clear out_pkt_rdy (bit0) bit .5-.4 reserved .3 stall signal receive bit 0 mcu can clear this bit 1 sie sets this bit after sending stall packet .2 fifo flush bit 0 no effect (when write) 1 fifo is flushed, and in_pkt_rdy cleared .1 force stall bit 0 mcu clears this bit to end the stall condition 1 issues a stall handshake to usb .0 out packet ready bit 0 no effect (when write) 1 sie sets this bit once a valid data is written to the fifo
control registers s3c9664/p9664 (p reliminary s pec ) 4- 16 epmode? endpoint mode register page 0, e7h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 reset length 0 0 22.4 m s + a 0 1 12.0 m s + a 1 0 6.0 m s + a 1 1 4.0 m s + a note: a @ 0.66 m s .5 - .2 reserved .1 endpoint 2 mode 0 endpoint 2 acts as an in interrupt endpoint 1 endpoint 2 acts as an out interrupt endpoint .0 endpoint 1 mode 0 endpoint 1acts as an in interrupt endpoint 1 endpoint 1 acts as an out interrupt endpoint
s3c9664/p9664 (p reliminary s pec ) control registers 4- 17 flags ? system flags register page 0, d5h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 ? ? ? ? read/write r/w r/w r/w r/w ? ? ? ? .7 carry flag (c) 0 operation does not generate a carry or borrow condition .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is +127 or 3 ?128 1 operation result is 3 +127 or ?128 .3 ? .0 not used for s3c9664
control registers s3c9664/p9664 (p reliminary s pec ) 4- 18 p0conh ? port 0 control high byte register page 0, e7h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 0, p0.7/int0 configuration bits 0 0 schmitt trigger input; interrupt on falling edges 0 1 schmitt trigger input; interrupt on rising edges 1 0 n-ch open drain output 1 1 push-pull output .5 and .4 port 0, p0.6/int0 configuration bits 0 0 schmitt trigger input; interrupt on falling edges 0 1 schmitt trigger input; interrupt on rising edges 1 0 n-ch open drain output 1 1 push-pull output .3 and .2 port 0, p0.5/int0 configuration bits 0 0 schmitt trigger input; interrupt on falling edges 0 1 schmitt trigger input; interrupt on rising edges 1 0 n-ch open drain output 1 1 push-pull output .1 and .0 port 0, p0.4/int0 configuration bits 0 0 schmitt trigger input; interrupt on falling edges 0 1 schmitt trigger input; interrupt on rising edges 1 0 n-ch open drain output 1 1 push-pull output
s3c9664/p9664 (p reliminary s pec ) control registers 4- 19 p0conl ? port 0 control low byte register page 0, e6h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 0, p0.3/int0 configuration bits 0 0 schmitt trigger input; interrupt on falling edges 0 1 schmitt trigger input; interrupt on rising edges 1 0 n-ch open drain output 1 1 push-pull output .5 and .4 port 0, p0.2/int0 configuration bits 0 0 schmitt trigger input; interrupt on falling edges 0 1 schmitt trigger input; interrupt on rising edges 1 0 n-ch open drain output 1 1 push-pull output .3 and .2 port 0, p0.1/int0 configuration bits 0 0 schmitt trigger input; interrupt on falling edges 0 1 schmitt trigger input; interrupt on rising edges 1 0 n-ch open drain output 1 1 push-pull output .1 and .0 port 0, p0.0/int0 configuration bits 0 0 schmitt trigger input; interrupt on falling edges (or capture input) 0 1 schmitt trigger input; interrupt on rising edges 1 0 n-ch open drain output 1 1 alternative function (t0 out : match or pwm)
control registers s3c9664/p9664 (p reliminary s pec ) 4- 20 p0int ? port 0 interrupt enable register page 0, eah bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 p0.7/int0 interrupt enable bit 0 disable p0.7 interrupt 1 enable p0.7 interrupt .6 p0.6/int0 interrupt enable bit 0 disable p0.6 interrupt 1 enable p0.6 interrupt .5 p0.5/int0 interrupt enable bit 0 disable p0.5 interrupt 1 enable p0.5 interrupt .4 p0.4/int0 interrupt enable bit 0 disable p0.4 interrupt 1 enable p0.4 interrupt .3 p0.3/int0 interrupt enable bit 0 disable p0.3 interrupt 1 enable p0.3 interrupt .2 p0.2/int0 interrupt enable bit 0 disable p0.2 interrupt 1 enable p0.2 interrupt .1 p0.1/int0 interrupt enable bit 0 disable p0.1 interrupt 1 enable p0.1 interrupt .0 p0.0/int0 interrupt enable bit 0 disable p0.0 interrupt 1 enable p0.0 interrupt
s3c9664/p9664 (p reliminary s pec ) control registers 4- 21 p0pnd ? port 0 interrupt pending register page 0, ebh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write (note) r/w r/w r/w r/w r/w r/w r/w r/w .7 p0.7/int0 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) .6 p0.6/int0 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) .5 p0.5/int0 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) .4 p0.4/int0 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) .3 p0.3/int0 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) .2 p0.2/int0 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) .1 p0.1/int0 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) .0 p0.0/int0 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) note: to clear a port 0 interrupt pending condition, write a "0" to the corresponding p0pnd register bit location.
control registers s3c9664/p9664 (p reliminary s pec ) 4- 22 p0purh ? port0 pull-up/down enable register (high byte) page 0, e5h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 0.7 pull-up/down bits 0 0 enable pull-up 0 1 enable pull-down 1 0 disable pull-up/down 1 1 disable pull-up/down .5 and .4 port 0.6 pull-up/down bits 0 0 enable pull-up 0 1 enable pull-down 1 0 disable pull-up/down 1 1 disable pull-up/down .3 and .2 port 0.5 pull-up/down bits 0 0 enable pull-up 0 1 enable pull-down 1 0 disable pull-up/down 1 1 disable pull-up/down .1 and .0 port 0.4 pull-up/down bits 0 0 enable pull-up 0 1 enable pull-down 1 0 disable pull-up/down 1 1 disable pull-up/down note: pull ?up/down resister is to be automatically disabled on push-pull output mode and open-drain output mode. otherwise, which can be enabled in all input modes
s3c9664/p9664 (p reliminary s pec ) control registers 4- 23 p0purl ? port 0 pull-up/down enable register (low byte) page 0, e4h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 0.3 pull-up/down bits 0 0 enable pull-up 0 1 enable pull-down 1 0 disable pull-up/down 1 1 disable pull-up/down .5 and .4 port 0.2 pull-up/down bits 0 0 enable pull-up 0 1 enable pull-down 1 0 disable pull-up/down 1 1 disable pull-up/down .3 and .2 port 0.1 pull-up/down bits 0 0 enable pull-up 0 1 enable pull-down 1 0 disable pull-up/down 1 1 disable pull-up/down .1 and .0 port 0.0 pull-up/down bits 0 0 enable pull-up 0 1 enable pull-down 1 0 disable pull-up/down 1 1 disable pull-up/down note : pull ?up/down resister is to be automatically disabled on push-pull output mode and open drain output mode . otherwise, which can be enabled in all input modes.
control registers s3c9664/p9664 (p reliminary s pec ) 4- 24 p1conh ? port 1 control high byte register page 0, e9h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 1, p1.7/int1 configuration bits 0 0 input, falling edge external interrupt with pull-up resistor 0 1 input, rising edge external interrupt 1 0 n-ch open drain out 1 1 push-pull output .5 and .4 port 1, p1.6/int1 configuration bits 0 0 input, falling edge external interrupt with pull-up resistor 0 1 input ,rising edge external interrupt 1 0 n-ch open drain out 1 1 push-pull output .3 and .2 port 1, p1.5/ad5 /int1 configuration bits 0 0 input, falling edge external interrupt pull-up resistor enabled; a/d converter off 0 1 input; a/d converter off, rising edge external interrupt 1 0 a/d converter input (ad5); input off 1 1 push-pull output .1 and .0 port 1, p1.4/ad4/int1 configuration bits 0 0 input, falling edge external interrupt pull-up resistor enabled; a/d converter off 0 1 input; a/d converter off, rising edge external interrupt 1 0 a/d converter input (ad4); input off 1 1 push-pull output
s3c9664/p9664 (p reliminary s pec ) control registers 4- 25 p1conl ? port 1 control low byte register page 0, e8h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 1, p1.3/ad3/int1 configuration bits 0 0 input, falling edge external interrupt pull-up resistor enabled; a/d converter off 0 1 input; a/d converter off, rising edge external interrupt 1 0 a/d converter input (ad3); input off 1 1 push-pull output .5 and .4 port 1, p1.2/ad2 /int1 configuration bits 0 0 input, falling edge external interrupt pull-up resistor enabled; a/d converter off 0 1 input; a/d converter off, rising edge external interrupt 1 0 a/d converter input (ad2); input off 1 1 push-pull output .3 and .2 port 1, p1.1/ad1/int1 configuration bits 0 0 input, falling edge external interrupt pull-up resistor enabled; a/d converter off 0 1 input; a/d converter off ,rising edge external interrupt 1 0 a/d converter input (ad1); input off 1 1 push-pull output .1 and .0 port 1, p1.0/ad0/int1 configuration bits 0 0 input, falling edge external interrupt pull-up resistor enabled; a/d converter off 0 1 input; a/d converter off, rising edge external interrupt 1 0 a/d converter input (ad0); input off 1 1 push-pull output
control registers s3c9664/p9664 (p reliminary s pec ) 4- 26 p1int ? port 1 interrupt enable register page 0, ech bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 p1.7/int1 interrupt enable bit 0 disable p1.7 interrupt 1 enable p1.7 interrupt .6 p1.6/int1 interrupt enable bit 0 disable p1.6 interrupt 1 enable p1.6 interrupt .5 p1.5/int1 interrupt enable bit 0 disable p1.5 interrupt 1 enable p1.5 interrupt .4 p1.4/int1 interrupt enable bit 0 disable p1.4 interrupt 1 enable p1.4 interrupt .3 p1.3/int1 interrupt enable bit 0 disable p1.3 interrupt 1 enable p1.3 interrupt .2 p1.2/int1 interrupt enable bit 0 disable p1.2 interrupt 1 enable p1.2 interrupt .1 p1.1/int1 interrupt enable bit 0 disable p1.1 interrupt 1 enable p1.1 interrupt .0 p1.0/int1 interrupt enable bit 0 disable p1.0 interrupt 1 enable p1.0 interrupt
s3c9664/p9664 (p reliminary s pec ) control registers 4- 27 p1pnd ? port 1interrupt pending register page 0, edh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write (note) r/w r/w r/w r/w r/w r/w r/w r/w .7 p1.7/int1 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) .6 p1.6/int1 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) .5 p1.5/int1 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) .4 p1.4/int1 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) .3 p1.3/int1 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) .2 p1.2/int1 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) .1 p1.1/int1 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) .0 p1.0/int1 interrupt pending bit 0 no interrupt pending (when bit is read) 1 interrupt is pending (when bit is read) note: to clear a port 1 interrupt pending condition, write a "0" to the corresponding p1pnd register bit location.
control registers s3c9664/p9664 (p reliminary s pec ) 4- 28 p2conint ? port 2 control/interrupt register page 0, efh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 2, p2.1/int2configuration bits 0 0 input, rising edge external interrupt 0 1 input, falling edge external interrupt with pull-up resister 1 0 n-ch open drain out 1 1 push-pull output .5 and .4 port 2, p2.0/int2 configuration bits 0 0 input, rising edge external interrupt 0 1 input, falling edge external interrupt with pull-up resister 1 0 n-ch open drain out 1 1 push-pull output .3 and .2 p2.0-p2.1 interrupt enable bits 0 external interrupt disable 1 external interrupt enable .1 and .0 p2.0-p2.1 interrupt pending bits 0 no pending (when read)/clear pending bit 1 pending (when read)/no effect (when write)
s3c9664/p9664 (p reliminary s pec ) control registers 4- 29 pwrmgr ? usb power management register page 0, f8h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 ? . 5 reserved .4 vpin value bit 0 indicates the value of vpin is low 1 indicates the value of vpin is high .3 vmin value bit 0 indicates the value of vmin is low 1 indicates the value of vmin is high .2 clear suspend counter 0 no effect 1 clear suspend counter .1 resume signal sending bit 0 resume signal is ended 1 while in suspend state, if the mcu wants to initiate a resume, it writes a 1 to this register for 10 ms (maximum of 15 ms), and clears this register. in suspend mode, if this bit is set to "1", usb generates resume signaling. .0 suspend status bit 0 cleared automatically when mcu writes a zero to resume signal sending bit or when function receives resume signal from the host while in suspend mode 1 this bit is set when suspend interrupt occur
control registers s3c9664/p9664 (p reliminary s pec ) 4- 30 subcon ? sub_oscillator control page 0, efh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 ? ? 0 0 0 0 read/write r/w r/w ? ? r/w r/w r/w r/w .7 sub_oscillator interrupt enable bit 0 sub_oscillator interrupt disable 1 sub_oscillator interrupt enable .6 sub_oscillator interrupt pending bit 0 no pending (when read)/clear pending (when write) 1 pending (when read)/no effect (when write) .5 sub_oscillator counter clear bit 0 no effect/ after counter cleared ,automatically this bit is then cleared to ?0? 1 clear sub_oscillator counter clear sub_oscillator enable bit .4 0 sub_oscillator disable 1 sub_oscillator enable sub_oscillator counter input clock selection bits .3 and .1 0 0 0 f osc /2048 0 0 1 f osc /3072 0 1 0 f osc /4096 0 1 1 f osc /6144 1 0 0 f osc /8192 1 0 1 f osc /12288 1 1 0 f osc /16384 1 1 1 f osc /24576 .0 not used for s3c9664 note: f osc = 158.86 khz ( 10 %)
s3c9664/p9664 (p reliminary s pec ) control registers 4- 31 sym ? system mode register page 0, dfh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7 ? .4 not used for s3c9664 .3 global interrupt enable bit 0 g lobal interrupt processing disable 1 g lobal interrupt processing enable .2 and .0 page select bit 0 0 0 page 0 0 0 1 page 1 0 1 0 page 2 (not allowed in s3c9664) 0 0 1 page 3 (not allowed in s3c9664)
control registers s3c9664/p9664 (p reliminary s pec ) 4- 32 t0con ? timer 0 control register page 0, d2h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? .7 and .6 t0 counter input clock selection bits 0 0 f osc /4096 0 1 f osc /256 1 0 f osc / 8 1 1 f osc /1 .5 and .4 t0 operating mode selection bits 0 0 interval timer mode 0 1 capture mode (capture on falling edge, counter running, ovf) 1 0 capture mode (capture on rising edge, counter running, ovf) 1 1 pwm mode (ovf interrupt can occur) .3 t0 counter clear bit 0 no effect 1 clear the timer 0 counter (when write) .2 and .0 not used for s3c9664
s3c9664/p9664 (p reliminary s pec ) control registers 4- 33 t0int ? timer 0 interrupt control register page 0, d3h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r r r r r/w r/w r/w r/w .7 and .4 not used for s3c9664 .3 t0 overflow interrupt 0 disable t0ovf interrupt 1 enable toovf interrupt .2 t0 match/capture interrupt enable bit 0 disable t0int interrupt 1 enable t0int interrupt .1 t0 overflow interrupt pending bit 0 no interrupt pending 0 clear this pending bit (write) 1 interrupt is pending .0 t0 interrupt pending bit (capture or match interrupt) 0 no interrupt pending 0 clear this pending bit (write) 1 interrupt is pending
control registers s3c9664/p9664 (p reliminary s pec ) 4- 34 t1con ? timer 1 control register page 0, e3h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r r r/w r/w r/w r/w .7 and .6 t1 input clock selection bits 0 0 f osc /10246 0 1 f osc /256 1 0 f osc /64 1 1 f osc /8 .5 and .4 not used for s3c9664 .3 t1 counter clear bit 0 no effect 1 clear the timer 0 counter (when write) .2 t1 counter enable bit 0 disable counting operation 1 enable counting operation .1 t1 interrupt enable bit 0 disable interrupt 1 enable interrupt .0 t1 interrupt pending bit 0 no interrupt pending 0 clear this pending bit (write) 1 interrupt is pending
s3c9664/p9664 (p reliminary s pec ) control registers 4- 35 usbcon ? usb control register page 0, f eh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7- .6 reserved .5 dp/dm control bit 0 dp/dm can not be individually controlled by mcu 1 dp/dm can be individually controlled by mcu to set usbcon.4 and usbcon.3 .4 dp status bit 0 dp is low 1 dp is high .3 dm status bit 0 dm is low 1 dm is high .2 usb reset mcu bit 0 usb which is been on reset can not make mcu reset 1 usb which is been on reset can be able to reset mcu .1 mcu reset usb bit 0 no effect 1 mcu forces usb be reset .0 usb reset signal receive bit 0 clear reset signal bit 1 this bit is set when host send usb rest signal
control registers s3c9664/p9664 (p reliminary s pec ) 4- 36 usbint ? usb interrupt enable register page 0, f7h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? 0 1 0 1 1 read/write ? ? ? r/w r/w r/w r/w r/w .7 ? . 5 not used for s3c9664 .4 usb reset interrupt enable bit 0 disable usb reset interrupt 1 enable usb reset interrupt .3 endpoint 2 interrupt enable bit 0 disable endpoint 2 interrupt 1 enable endpoint 2 interrupt (default) .2 suspend/resume interrupt enable bit 0 disable suspend and resume interrupt (default) 1 enable suspend and resume interrupt .1 endpoint1 interrupt enable bit 0 disable endpoint 1 interrupt 1 enable endpoint 1 interrupt (default) .0 endpoint0 interrupt enable bit 0 disable endpoint 0 interrupt 1 enable endpoint 0 interrupt (default)
s3c9664/p9664 (p reliminary s pec ) control registers 4- 37 usbpnd ? usb interrupt pending register page 0, f6h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7 ?.6 not used for s3c9664 .5 usb reset interrupt pending bit 0 no effect (once read, this bit is cleared automatically) 1 this bit is set, when usb reset need to served .4 endpoint interrupt pending bit 0 no effect (once read, this bit is cleared automatically) 1 this bit is set, when endpoint 2 need to served .3 resume interrupt pending bit 0 no effect (once read, this bit is cleared automatically) 1 this bit is set, if resume signaling is received while in suspend mode .2 suspend interrupt pending bit 0 no effect (once read, this bit is cleared automatically) 1 this bit is set, when suspend signaling is received .1 endpoint1 interrupt pending bit 0 no effect (once read, this bit is cleared automatically) 1 this bit is set, when endpoint1 needs to be serviced .0 endpoint0 interrupt pending bit 0 no effect (once read, this bit is cleared automatically) 1 this bit is set, while endpoint 0 needs to serviced. it is set under the following conditions: ? out_pkt_rdy is set ? in_pkt_rdy get cleared ? sent_stall gets set ? data_end gets cleared ? setup_end gets set
control registers s3c9664/p9664 (p reliminary s pec ) 4- 38 xcon ? usb signal control register page 1, feh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? 0 0 0 0 0 0 read/write ? ? w w w w w w .7 pull-up resister at (d- ) enable bit 0 pull-up resister at (d-) disable 1 pull-up resister at (d+) enable .6 gpio or usb port select bit 0 general in/out port enable 1 usb port enable .6 ? . 5 this register will be used to control the usb signal quality. the usb signal (d+/d-) of transceiver can be changed by setting this register. note: dly means delay time of rising/fallling time. num hex value 1 2 3 4 5 0x00 0x38 0x3c 0x3d 0x3e result, dm default value, 0.88 v, 1.19 v 1.58 v, 1.55 v 1.50 v, 1.50 v 1.65 v, 1.65 v 1.80 v, 1.80 v good note: this value is only for otp products. xcon is a write-only register and can be accessed through page 1. edge control bit 5, 2 bit 4, 1 bit 3, 0 dly value unit about 2.5 nsec 0 0 1 0 1 1 0 1 dly 0 dly 1 dly 2 dly 4 0 rise edge 1 1 1 0 0 0 0 1 dly 4 dly 2 dly 1 dly 0 1 fall edge x x x x 5 4 3 2 1 0 bit dm dp (v dd = 5.12 v) x - point 1 x - point 2 dp dm dp
s3c9664/p9664 (p reliminary s pec ) interrupt structure 5- 1 5 interrupt structure overview the sam88rcri interrupt structure has two basic components: a vector, and sources. the number of interrupt sources can be serviced through a interrupt vector which is assigned in rom address 0000h?0001h. sources vector s1 s2 s3 sn 0000h 0001h notes: 1. the sam88rcri interrupt has only one vector address (0000h-0001h). 2. the number of sn value is expandable. figure 5- 1 . s3c9 -series interrupt type interrupt processing control points interrupt processing can be controlled in two ways: globally, or by specific interrupt level and source. the system- level control points in the interrupt structure are therefore: ? global interrupt enable and disable (by ei and di instructions) ? interrupt source en able and disable settings in the corresponding peripheral control register(s) enable/disable interrupt instructions (ei, di) the system mode register, sym (dfh), is used to enable and disable interrupt processing. sym.3 is the enable and disable bit for global interrupt processing, which you can set by modifying sym.3 . an enable interrupt (ei) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. al though you can manipulate sym.3 directly to enable and disable interrupts during normal operation, we recommend that you use the ei and di instructions for this purpose.
interrupt structure s 3c9664/p9664 (p reliminary s pec ) 5- 2 interrupt pending function types when the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (iret) occurs. interrupt priority because there is not a interrupt priority register in sam87r i , the order of service is determined by a sequence of source which is executed in interrupt service routine. s r q interrupt pending register global interrupt control (ei, di instruction) vector interrupt cycle interrpt priority is determind by software polling method "ei" instruction execution reset source interrupts source interrupt enable figure 5- 2 . interrupt function diagram
s3c9664/p9664 (p reliminary s pec ) interrupt structure 5- 3 interrupt source service sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request pending bit to "1". 2. the cpu generates an interrupt acknowledge signal. 3. the service routine starts and the source's pending flag is cleared to "0" by software. 4. interrupt priority must be determined by software polling method. interrupt service routines before an interrupt request can be serviced, the following conditions must be met: ? interrupt proce ssing must be enabled (ei, sym.3 = "1") ? interrupt must be enabled at the interrupt's source (peripheral control register) if all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the global interrupt enable bit in the sym register (di, sym. 3 = "0") to disable all subsequent interrupts. 2. save the program counter and status flags to stack. 3. branch to the interrupt vector to fetch the service routine's address. 4. pass control to the interrupt service rout ine. when the interrupt service routine is completed, an interrupt return instruction (iret) occurs. the iret restores the pc and status flags and sets sym.3 to "1"(ei), allowing the cpu to process the next interrupt request. generating interrupt vector addresses the interrupt vector area in the rom contains the address of the interrupt service routine. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to sta ck. 2. push the program counter's high-byte value to stack. 3. push the flags register values to stack. 4. fetch the service routine's high-byte address from the vector address 0000h. 5. fetch the service routine's low-byte address from the vector address 0001h. 6. branch to the service routine specified by the 16-bit vector address.
interrupt structure s 3c9664/p9664 (p reliminary s pec ) 5- 4 s3c9664 interrupt structure the s3c9664 microcontroller has thirteen peripheral interrupt sources: ? timer 0 match interrupt ? timer 0 overflow interrupt ? timer 1 match interrupt ? suspend interrupt ? resume interrupt ? internal rc interrupt ? usb reset interrupt ? three endpoint interrupts for endpoint 0, endpoint 1 and endpoint 2 ? eight external interrupts for port 0 , p 0 .0?p 0 . 7 ? eight external interrupts for port 1 , p 1 . 1 ?p 1 . 7 ? two external interrupts for port 2, p2.0?p2.1
s3c9664/p9664 (p reliminary s pec ) interrupt structure 5- 5 t0int.2 vector 0000h sym.3 (ei, di) p0.0-p0.7 interrupt p1.0-p1.7 interrupt subcon.6 p0pnd.0-7 p1pnd.0-7 internal rc interrupt subcon.7 p0int.x p1int.x t0int.0 resume interrupt t0int.1 t0int.3 match/capture interrupt overflow interrupt endpoint 0 interrupt ep0_pnd enable_ep0 resume_ pnd suspend/resume interrupt enable suspend interrupt endpoint 1 interrupt ep1_pnd enable_ep1 suspend_ pnd timer 1 match interrupt t1con.0 t1con.1 p2conint .2-.3 p2.0-p2.1 interrupt p2conint.0-.1 endpoint 2 interrupt ep2_pnd enable_ep2 usb_rst interrupt usb_rst enable_usb_rst figure 5- 3 . s3c9664 interrupt structure
s3c9664/p9664 (p reliminary s pec ) clock circuit 7 - 1 7 clock circuit overview the s3c9664 has two oscillation circuit options, a crystal/ceramic oscillation and an external clock source. the crystal or ceramic oscillation source provides a maximum 6 mhz clock. the x in and x out pins connect the oscillation source to the on-chip clock circuit. external clock and crystal/ceramic oscillator circuits are shown in figures 7- 1 and 7- 2. s3c9664 x out x in figure 7-1. external oscillator s3c9664 x out x in figure 7- 2 . main oscillator circuit (crystal/ceramic oscillator) main oscillator logic to increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator circuit. for this reason, very high resolution waveforms (square signal edges) must be generated in order for the cpu to efficiently process logic operations. clock status during power-down modes the two power-down modes, stop mode and idle mode, affect clock oscillation as follows: ? in stop mode, the main oscillator "freezes," halting the cpu and peripherals. the contents of the register file and current system register values are retained. reset operation releases the stop mode , and starts the oscillator . ? in idle mode, the internal clock signal is gated off to the cpu, but not to interrupt control and the timer. the current cpu status is preserved, including stack pointer, program counter, and flags. data in the register file is retained. idle mode is released by a reset or by an interrupt (external or internally-generated).
clock circuit s3c9664/p9664 (p reliminary s pec ) 7 - 2 system clock control register (clkcon) the system clock control register, clkcon, is located in location d4h. it is read/write addressable and has the following functions: ? oscillator irq wake-up function enable/disable (clkcon.7) ? oscillator frequency divide-by value: non-divided, 2, 8, or 16 (clkcon.4 and clkcon.3) the clkcon register controls whether or not an external interrupt can be used to trigger a stop mode release (this is called the "irq wake-up" function). the irq wake-up enable bit is clkcon.7. after a reset , the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the f osc /16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can then increase the cpu clock speed to f osc , f osc /2 or f osc /8. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb system clock control register (clkcon) d4h, r/w no effect divide-by selection bits for cpu clock frequency: 00 = fosc/16 01 = fosc/8 10 = fosc/2 11 = fosc(non-divided) oscillator irq wake-up enable bit: 0 = enable irq for main system oscillator wake-up function 1 = disable irq for main system oscillator wake-up function no effect figure 7- 3 . system clock control register (clkcon)
s3c9664/p9664 (p reliminary s pec ) clock circuit 7 - 3 main osc noise filter oscillator wake-up oscillator stop clkcon.7 int pin clkcon.4-.3 1/2 1/8 1/16 m u x stop instruction cup clock figure 7- 4 . system clock circuit diagram
s3c9664/p9664 (p reliminary s pec ) reset reset and power-down 8 - 1 8 reset reset and power-down system reset overview comparator glitch filter reset reference voltage generator voltage divider start up notes: 1. start up circuit: start up reference voltage generator circuit when device powered. 2. reference voltage generator: supply voltage independent reference voltage generator. (supply voltage must great then 2.5 v) 3. voltage divider: divide supply voltage by "n" (n: integer, 2). 4. comparator: compare reference voltage and divided voltage. 5. glitch filter: remove glitch and noise signal. figure 8-1. lvd characteristcs
reset reset and power-down s3c9664/p9664 (p reliminary s pec ) 8 - 2 vc (compare voltage) reference voltage divide voltage v dd (supply voltage) normal operation reset operation by lvd notes: 1. lvd operation voltage range: 2.3 v-6.0 v 2. lvd detection voltage range: 3.4 v 0.4 v 3. lvd current consumption: less then 10 ua (normally 5 ua) 4. lvd powered reset release time: more then 500 usec (lvd only, typical) 5. lvd simulation conditions (hspice simulation) temp: -40 - 80 c process veriation: worst to best conditions test voltage: 0.0 v-7.0 v powered slew rate: 5 v/1 usec- 5 v/10 msec figure 8-2. lvd architecture the fol lowing sequence of events occur during a reset operation: ? all interrupts are disabled. ? the watchdog function (basic timer) is enabled. ? ports 0 and 1 are set to schmitt trigger input mode and all pull-up resistors are disabled. ? peripheral control and data registers are disabled and reset to their initial values. ? the program counter is loaded with the rom reset address, 0100h. ? when the programmed oscillation stabilization time interval has elapsed, the address stored in rom location 0100h (and 0101h) is fetched and executed. note to program the duration of the oscillation stabilization interval, you must make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010b ' to the upper nibble of btcon.
s3c9664/p9664 (p reliminary s pec ) reset reset and power-down 8 - 3 power-down modes stop mode stop mode is invoked by the instruction stop ( opcode 7fh). in stop mode, the operation of the cpu and all peripherals is halted. that is, the on-chip main oscillator stops and the supply current is reduced to less than 1 20 a. all system functions are halted when the clock "freezes," but data stored in the internal register file is retained. stop mode can be released in one of two ways: by a reset signal or by an external interrupt. using reset reset to release stop mode stop mode is released when the reset signal is released and returns to high level. all system and peripheral control registers are then reset to their default values and the contents of all data registers are retained. reset operation automatically selects a slow clock (1/16) because clkcon.3 and clkcon.4 are cleared to '00b'. after the oscillation stabilization interval has elapsed, the cpu executes the system initialization routine by fetching the 16-bit address stored in rom locations 0100h and 0101h. using an external interrupt to release stop mode only external interrupts with an rc-delay noise filter circuit can be used to release stop mode (clock-related external interrupts cannot be used). external interrupts in the ks86c6504/6508 interrupt structure does not meet this criteria. note that when stop mode is released by an external interrupt, the current values in system and peripheral control registers are not changed. when you use an interrupt to release stop mode, the clkcon.3 and clkcon.4 register values remain unchanged, and the currently selected clock value is used. if you use an external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must make the appropriate control and clock settings before entering stop mode. the external interrupt is serviced when the stop mode release occurs. following the iret from the service routine, the instruction immediately following the one that initiated stop mode is executed. note do not use the stop mode when external clock source is being used as the oscillation circuit option. idle mode idle mode is invoked by the instruction idle ( opcode 6fh). in idle mode, cpu operations are halted while select peripherals remain active. during idle mode, the internal clock signal is gated off to the cpu, but not to interrupt logic and timer/counters. port pins retain the mode (input or output) they had at the time idle mode was entered. there are two ways to release idle mode: 1. execute reset . all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects a slow clock (1/16) because clkcon.3 and clkcon.4 are cleared to '00b'. if interrupts are masked, reset is the only way to release idle mode. 2. activate any enabled interrupt, causing idle mode to be released. when you use an interrupt to release idle mode, the clkcon.3 and clkcon.4 register values remain unchanged, and the currently selected clock value is used. the interrupt is then serviced. following the iret from the service routine, the instruction immediately following the one that initiated idle mode is executed. note only external interrupts that are not clock-related can be used to release stop mode. to release idle mode, however, any type of interrupt (that is, internal or external) can be used.
reset reset and power-down s3c9664/p9664 (p reliminary s pec ) 8 - 4 hardware reset reset values tables 8- 1 through 8- 3 list the values for cpu and system registers, peripheral control registers, and peripheral data registers following a reset operation in normal operating mode. the following notation is used in these tables to represent specific reset values: ? a "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. ? an 'x' means that the bit value is undefined following reset . ? a dash (' ?') means that the bit is either not used or not mapped. table 8-1. register map and reset status (page 0) register name mnemonic address bit values after reset reset 7 6 5 4 3 2 1 0 g eneral purpose register file & stack area ? 00 ? 7 fh x x x x x x x x working register area ? c0h?cfh x x x x x x x x timer 0 counter register t0cnt d0h 0 0 0 0 0 0 0 0 timer 0 data register t0data d1h 1 1 1 1 1 1 1 1 timer 0 control register t0con d2h 0 0 0 0 0 0 0 0 timer 1 interrupt control register t0int d3h 0 0 0 0 0 0 0 0 clock control register clkcon d4h 0 0 0 0 0 0 0 0 system flags register flags d5h 0 0 0 0 ? ? ? ? a/d converter data register(high byte) addatah d6h x x x x x x x x a/d converter data register (low byte) addatal d7h ? ? ? ? ? ? x x a/d control register adcon d8h ? 0 0 0 0 0 0 0 stack pointer register sp d9h x x x x x x x x port 2 data register p2 dah 0 0 0 0 0 0 0 0 location dbh is not mapped. basic timer control register btcon dch 0 0 0 0 0 0 0 0 basic timer counter btcnt ddh 0 0 0 0 0 0 0 0 location deh is not mapped. system mode register sym dfh ? ? ? ? 0 0 0 0 note : ? : not mapped, x: undefined
s3c9664/p9664 (p reliminary s pec ) reset reset and power-down 8 - 5 table 8-1. register map and reset status (page 0) (c ontinued) register name mnemonic address bit values after reset reset 7 6 5 4 3 2 1 0 port 0 data register p0 e0h 0 0 0 0 0 0 0 0 port 1 data register p1 e1h 0 0 0 0 0 0 0 0 timer 1 counter register t1cnt e2h 0 0 0 0 0 0 0 0 timer 1 control register t1con e3h 0 0 0 0 0 0 0 0 port 0 pull-up/down register (low byte) p0purl e4h 0 0 0 0 0 0 0 0 port 0 pull-up/down register (high byte) p0purh e5h 0 0 0 0 0 0 0 0 port 0 control register (low byte) p0conl e6h 0 0 0 0 0 0 0 0 port 0 control register (high byte) p0conh e7h 0 0 0 0 0 0 0 0 port 1 control register (low byte) p1conl e8h 0 0 0 0 0 0 0 0 port 1 control register (high byte) p1conh e9h 0 0 0 0 0 0 0 0 port 0 interrupt enable register p0int eah 0 0 0 0 0 0 0 0 port 0 interrupt pending register p0pnd ebh 0 0 0 0 0 0 0 0 port 1 interrupt enable register p1int ech 0 0 0 0 0 0 0 0 port 1 interrupt pending register p1pnd edh 0 0 0 0 0 0 0 0 timer 1 data register t1data eeh 1 1 1 1 1 1 1 1 port 2 control/interrupt register p2conint efh 0 0 0 0 0 0 0 0 usb function address register faddr f0h 0 0 0 0 0 0 0 0 usb control endpoint status register ep0csr f1h 0 0 0 0 0 0 0 0 usb interrupt endpoint 1 status register ep1csr f2h 0 1 0 0 0 0 0 0 usb control endpoint byte count register ep0bcnt f3h 0 0 0 0 0 0 0 0 usb control endpoint fifo register ep0fifo f4h x x x x x x x x usb interrupt endpoint 1 fifo register ep1fifo f5h x x x x x x x x usb interrupt pending register usbpnd f6h 0 0 0 0 0 0 0 0 usb interrupt enable register usbint f7h 0 0 0 0 1 0 1 1 usb power management register pwrmgr f8h 0 0 0 0 0 0 0 0 usb interrupt endpoint 2 status register ep2csr f9h 0 1 0 0 0 0 0 0 usb interrupt endpoint 2 fifo register ep2fifo fah x x x x x x x x endpoint mode register epmode fbh 0 0 0 0 0 0 0 0 usb interrupt endpoint 1 byte count register ep1bcnt fch 0 0 0 0 0 0 0 0 usb control endpoint 2 byte count register ep2bcnt fdh 0 0 0 0 0 0 0 0 usb control register usbcon feh 0 0 0 0 0 0 0 0 sub oscillator control register subcon ffh 0 0 0 0 0 0 0 0
reset reset and power-down s3c9664/p9664 (p reliminary s pec ) 8 - 6 table 8-2. register map and reset status (page 1) register name mnemonic address bit values after reset reset 7 6 5 4 3 2 1 0 usb signal control register xcon feh 0 0 0 0 0 0 0 0
s3c9664/p9664 (p reliminary s pec ) i/o ports 9- 1 9 i/o ports overview the s3c9664 has three i/o ports (port 0, port 1, port2 only on usb disabled), 18 pins total. you can access these ports directly by writing or reading port data register addresses. table 9-1. s3c9664 port configuration overview port function description programmability p0.0-p0.7 bit-programmable i/o port for schmitt trigger input, push-pull output and n- ch open drain output. pull-up/pull-down resistors are assignable by software. port 1 pins can also be used as external interrupt. bit p1.0 ? p1.5 bit-programmable i/o port for schmitt trigger input, schmitt trigger input with pull-up and n- ch open drain output. port 1 pins can also be used as ad converter channel. bit p1.6 ? p1.7 bit-programmable i/o port for schmitt trigger input, schmitt trigger input with pull-up and n- ch open drain output and push-pull output. bit p2.0/d- ? p2.1/d+ bit-programmable i/o port for schmitt trigger input, schmitt trigger input with pull-up and n- ch open drain output and push-pull output. port 2 can be individually configured as external interrupt inputs. also it can be configured as an usb ports. bit
i/o ports s3c9664/p 9664 (p reliminary s pec ) 9- 2 port data registers table 9-2 gives you an overview of the port data register names, locations, and addressing characteristics. data registers for ports 0 and 1 have the structure shown in figure 9-1. table 9-2. port data register summary register name mnemonic hex r/w port 0 data register p0 e0h r/w port 1 data register p1 e1h r/w port 2 data register p2 fah r/w p0.4 p1.4 p0.3 p1.3 i/o port n data register (n = 0-2) .5 .4 .3 .2 .1 .0 msb lsb pn.1 p0.2 p1.2 pn.0 .6 .7 p0.5 p1.5 p0.6 p1.6 p0.7 p1.7 figure 9-1. port data register format
s3c9664/p9664 (p reliminary s pec ) i/o ports 9- 3 port 0 port 0 is bit-programmable, general-purpose, i/o ports. you can configure schmitt trigger input mode with rising edge external interrupt or falling edge external interrupt mode, n-channel open drain output and push pull output mode. meanwhile, pull-up and pull-down resister can be can be configured only on input modes . in normal operating mode, a reset clears the port 0 control registers (p0conh, p0conl, p0purh, p0purl) to ?00h?, configuring p0.0?p0.7 as schmitt trigger input, falling edge external interrupt with pull-up resister port 0 is accessed directly by writing or reading the port 0 data register. p0 (e0h, page 0). port 0 control register, high byte (p0conh) p0conh, e7h, r/w (page 0) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0.4 p0.6 p0conh 0 0 0 1 1 0 1 1 7,5,3,1 6,4,2,0 p0.7 p0.5 schmitt trigger input, falling edge external interrupt. schmitt trigger input, rising edge external interrupt. n-ch open drain output mode. push-pull output mode. port mode selection figure 9-2. port 0 control registers (p0conh) port 0 control register, low byte (p0conl) p0conl, e6h, r/w (page 0) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0.0 p0.2 p0conl 0 0 0 1 1 0 1 1 7,5,3,1 6,4,2,0 p0.3 p0.1 schmitt trigger input, falling edge external interrupt. (or capture input) schmitt trigger input, rising edge external interrupt. n-ch open drain output mode. alternative fuction (p0 output mode: match,pwm) port mode selection figure 9-3. port 0 control registers (p0conl)
i/o ports s3c9664/p 9664 (p reliminary s pec ) 9- 4 port 0 pull-up/down control registers p0purh, e5h, r/w, p0purl, e4h, r/w (page 0) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0.4 p0.6 p0purh p0.7 p0.5 p0.0 p0.2 p0purl p0.3 p0.1 0 0 0 1 1 0 1 1 7,5,3,1 enable pull-up enable pull-down disable pull-up/down disable pull-up/down port mode selection 6,4,2,0 figure 9-4. port 0 pull-up/down control registers (p0purh/p0purl)
s3c9664/p9664 (p reliminary s pec ) i/o ports 9- 5 port 1 port 1 is bit-programmable, general-purpose, i/o ports. you can configure schmitt trigger input mode, rising edge external interrupt with pull-up or falling edge external interrupt mode, n-channel open drain output (only for p1.7, p1.6) a/d converter input (only for p1.1-p1.5) and push pull output mode . in normal operating mode, a reset clears the port 0 control registers (p1conh, p1conl) to ?00h?, configuring p1.0?p1.7 as schmitt trigger input, falling edge external interrupt with pull-up resister. port 1 is accessed directly by writing or reading the port 1 data register. p1 (e1h, page 0). port 1 control register, high byte (p1conh) p1conh, e9h, r/w (page 0) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1.4 p1.6 p1conh p1.7 p1.5 0 0 0 1 1 0 1 1 7,5 6,4 schmitt trigger input, falling edge external interrupt with pull-up. schmitt trigger input, rising edge external interrupt. n-ch open drain output mode. push-pull output port mode selection 0 0 0 1 1 0 1 1 3,1 2,0 schmitt trigger input, falling edge external interrupt with pull-up. input,a/d converter off,rising edge external interrupt. a/d converter input ; input off push-pull output port mode selection figure 9-5. port 1 control register high byte (p1conh)
i/o ports s3c9664/p 9664 (p reliminary s pec ) 9- 6 port 1 control register, low byte (p1conl) p1conl, e8h, r/w (page 0) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1.0 p1.2 p1conl p1.3 p1.1 0 0 0 1 1 0 1 1 1 0 schmitt trigger input, falling edge external interrupt with pull-up. input,a/d converter off,rising edge external interrupt. a/d converter input ; input off push-pull output port mode selection figure 9-6. port 1 control register low byte (p1conl)
s3c9664/p9664 (p reliminary s pec ) i/o ports 9- 7 port 2 port 2 can be configured bit-programmable, general-purpose, i/o ports, only when usb ports are disabled (usbsel.0 = 0). otherwise (usbsel.1=1), port 2 is used for d+/d-. however, in general purpose i/0 port mode. you can configure schmitt trigger input mode, rising edge external interrupt and schmitt trigger input falling edge external interrupt mode with pull-up, n-channel open drain output and push pull output mode with pull-up. in normal operating mode, a reset clears the port 2 control registers (p2conint) to ?00h?, configuring p2.0?p2.1 as schmitt trigger input, rising edge external interrupt with pull-up resister. port 2 is accessed directly by writing or reading the port 2 data register. p2 (efh, page 0). port 2 control registers p2conint, efh, r/w (page 0) .3 .2 .1 .0 msb lsb p2.1-p2.0 interrupt enable bit p2.0 p2.1 p2conint: schmitt trigger input, rising edge external interrupt. schmitt trigger input, falling edge external interrupt with pull-up. n-channel open drain output mode. push-pull output mode with pull-up port mode selection 0 0 0 1 1 0 1 1 7, 5 6, 4 p2.1-p2.0 interrupt pending bit .7 .6 .5 .4 figure 9-7. port control registers (p2conint)
s3c9664/p9664 ( preliminary spec) basic timer and timer 0 10- 1 10 basic timer and timer 0 module overview the s3c9664 has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. the 8 -bit timer/counter is called timer 0. basic timer (bt) you can use the basic timer (bt) in two different ways: ? as a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction ? to signal the end of the required oscillation stabilization interval after a reset or a stop mode release. the functional components of the basic timer block are: ? clock frequency divider (f osc divided by 4096, 1024, or 128) with multiplexer ? 8-bit basic timer counter, btcnt (ddh, read-only) ? basic timer control register, btcon (dch, read/write) timer 0 timer 0 has three operating modes, one of which you select by the appropriate t0con setting: ? interval timer mode ? capture mode with a rising or falling edge trigger at the t0 pin ? pwm mode timer 0 has the following functional components: ? clock frequency divider (f osc divided by 4096, 256, 8, or 1) with multiplexer ? 8-bit counter (t0cnt), 8-bit comparator, and 8-bit reference data register (t0data) ? i/o pin (p1.0/t0) for timer 0 capture input or match output ? timer 0 overflow i nterrupt and match/capture interrupt generation ? timer 0 control register, t0con ? timer 0 interrupt control register, t0int
basic timer and timer 0 s3c9664/p9 664 ( preliminary spec) 10- 2 basic timer control register (btcon) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. it is located in set 1, address d3h, and is read/write addressable using register addressing mode. a reset clears btcon to "00h". this enables the watchdog function and selects a basic timer clock frequency of f osc /4096. to disable the watchdog function, you must write the signature code "1010b" to the basic timer register control bits btcon.7?btcon.4. the 8-bit basic timer counter, btcnt, can be cleared at any time during the normal operation by writing a "1" to btcon.1. to clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you write a "1" to btcon.0. basic timer control register (btcon) d3h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb divider clear bit for bt and t0: 0 = no effect 1 = clear both dividers basic timer counter clear bits: 0 = no effect 1 = clear btcnt watchdog timer enable bits: 1010b = disable watchdog function others = enable watchdog function basic timer input clock selection bits: 00 = f osc /4096 01 = f osc /1024 10 = f osc /128 11 = invalid selection figure 10-1. basic timer control register (btcon)
s3c9664/p9664 ( preliminary spec) basic timer and timer 0 10- 3 basic timer function description watchdog timer function you can program the basic timer overflow signal (btovf) to generate a reset by setting btcon.7?btcon.4 to any value other than "1010b". (the "1010b" value disables the watchdog function.) a reset clears btcon to "00h", automatically enabling the watchdog timer function. a reset also selects the cpu clock (as determined by the current clkcon register setting) divided by 4096 as the basic timer clock. a reset whenever a basic timer counter overflow occurs. during the normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. to do this, the btcnt value must be cleared (by writing a "1" to btcon.1) at regular intervals. if a system malfunction occurs due to circuit noise or some other error condition, the basic timer counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. in other words, during the normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, btcnt) is always broken by a btcnt clear instruction. if a malfunction does occur, a reset is triggered automatically. oscillation stabilization interval timer function you can also use the basic timer to program a specific oscillation stabilization interval after a reset or when stop mode has been released by an external interrupt. in stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. the btcnt value then starts increasing at the rate of f osc /4096 (for reset), or at the rate of the preset clock source (for an external interrupt). when btcnt.4 is set, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the cpu so that it can resume normal operation. in summary, the following events occur when stop mode is released: 1. during stop mode, a power-on reset or an external interrupt occurs to trigger the stop mode release and oscillation starts. 2. if a power-on reset occurred, the basic timer counter will increase at the rate of f osc /4096. if an external interrupt is used to release stop mode, the btcnt value increases at the rate of the preset clock source. 3. clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set. 4. when a btcnt.4 is set, no rmal cpu operation resumes. 5. figure 10-2 and 10-3 shows the oscillation stabilization time on reset and stop mode release
basic timer and timer 0 s3c9664/p9 664 ( preliminary spec) 10- 4 oscillation stabilization normal operating mode 0.8 v dd t wait = 4096x16x1/f osc basic timer increment and cpu operations are idle mode 10000b 00000b reset releasevoltage note: during of the oscillator stabilization wait time, t wait , when it is released by a power-on-reset is 4096x16/fosc. v dd reset internal reset release oscillator (x out ) btcnt clock btcnt value 0.8 v dd oscillator stabilization time figure 10-2. oscillation stabilization time on reset reset
s3c9664/p9664 ( preliminary spec) basic timer and timer 0 10- 5 note: duration of the oscillator stabilzation wait time, twait, it is released by an interrupt is determined by the setting in basic timer control register, btcon. v dd oscillation stabilization time reset external interrupt oscillator (x out ) btcnt clock btcnt value t wait basic timer increment 10000b stop release signal 00000b normal operating mode normal operating mode stop mode stop mode release signal stop instruction execution btcon.3 btcon.2 0 0 1 1 0 1 0 0 t wait 4096 x 16/fosc 1024 x 16/fosc 128 x 16/fosc invalid setting t wait (when f osc is 10 mhz) 6.55 ms 1.64 ms 0.2 ms figure 10-3. oscillation stabilization time on stop mode release
basic timer and timer 0 s3c9664/p9 664 ( preliminary spec) 10- 6 timer 0 control register (t0con) and interrupt control register(t0int) you use the timer 0 control register (t0con) and the timer 0 interrupt control register (t0int), to ? select the timer 0 operating mode (interval timer, capture mode, or pwm mode) ? select the timer 0 input clock frequency ? clear the timer 0 counter, t0cnt ? enable the timer 0 overflow interrupt and timer 0 match/capture interrupts ? clear timer 0 match/capture interrupt pending conditions t0con is located at address d2h and t0int at address d3h, both are read/write addressable using register addressing mode. a reset clears t0con and t0int to "00h". this sets timer 0 to normal interval timer mode, selects an input clock frequency of f osc /4096, and disables the timer 0 overflow interrupt and match/capture interrupts. you can clear the timer 0 counter at any time during the normal operation by writing a "1" to t0con.3. when a timer 0 overflow interrupt occurs and is serviced by the cpu, the pending condition is to be cleared by software. to enable the timer 0 match/capture interrupt, you must write t0int.2 to "1". to detect an interrupt pending condition, the application program polls t0int.0. when a "1" is detected, a timer 0 match/capture interrupt is pending. when the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, t0int.0. for a timer 0 overflow interrupt, like the way of handing timer 0 match/capture interrupt, you have to write t0int.3 to ?1? to be enabled. timer 0 overflower pending condition can be detected on the condition of toint.1 being set to ?1? when the application program polls t0int.1.and the pending condition must be cleared by software by writing t0int.1 a ?0? when the interrupt request has been serviced.
s3c9664/p9664 ( preliminary spec) basic timer and timer 0 10- 7 .7 .6 .5 .4 .3 .2 .1 .0 lsb msb timer 0 control register (t0con) d2h, r/w timer 0 input clock selection bits: 00 = f osc /4096 01 = f osc /256 10 = f osc /8 11 = f osc /1 timer 0 operating mode selection bits: 00 = interval mode 01 = capture mode (capture on falling edge, counter running, ovf can occur) 10 = capture mode (capture on rising edge, counter running, ovf can occur) 11 = pwm output (ovf interrupt can occur) timer 0 counter clear bit: 0 = no effect 1 = clear the timer 0 counter (when write) not used s3c9664. figure 10-4. timer 0 control register (t0con) timer 0 interrupt (t0int) pending bit: 0 = no interrupt 0 = clear pending bit (when write) 1 = interrupt is pending .7 .6 .5 .4 .3 .2 .1 .0 lsb msb timer 0 interrupt control register (t0int) d3h, r/w t0ovf enable bit: 0 = disable overflow 1 = enable overflow timer 0 overflow interrupt (t0ovf) pending bit: 0 = no interrupt 0 = clear pending bit (when write) 1 = interrupt is pending t0int enable bit: 0 = disable match/capture 1 = enable match/capture not used for s3c9664. figure 10-5. timer 0 interrupt control register (t0int)
basic timer and timer 0 s3c9664/p9 664 ( preliminary spec) 10- 8 timer 0 function description timer 0 interrupts the timer 0 module can generate two interrupts: the timer 0 overflow interrupt, and the timer 0 match/capture interrupt. a timer 0 overflow interrupt pending condition and a timer 0 match /capture interrupt pending condition must be cleared by software, however, by writing a "0" to the t0int.1 and t0int.0 pending bits. interval timer mode in interval timer mode, a match signal generates a timer 0 match interrupt and clears the counter. if you write the value "ffh" to the timer 0 reference data register, t0data, the counter will increment until an overflow occurs. (this condition is the same as normal counter operation.) data register (t0data) comparator match ctl t0con p0.0/t0 r (clear) pnd interrupt enable/disable t0_ovf counter (t0cnt) interrupt enable/disable t0_int clk pnd figure 10-6. simplified timer 0 function diagram: interval timer mode
s3c9664/p9664 ( preliminary spec) basic timer and timer 0 10- 9 match match match match match match match compare value (t0data) up counter value (t0cnt) 00h counter clear (t0con.3) interrupt request (t0con.0) clear clear clear count start t0con.3 1 t0data value change figure 10-7. timer 0 timing diagram
basic timer and timer 0 s3c9664/p9 664 ( preliminary spec) 10- 10 pulse width modulation mode the pwm cycle width (time) is determined the timer 0 input clock. one cycle is equal to t clk 2 8 (for the 8 -bit counter). the timer 0 data register value determines the pulse modulation width. (the minimum value is low level and the maximum value is high level.) a match signal generates the timer 0 interrupt (t0_int), but it does not clear the timer 0 counter value. data register (t0data) comparator ctl t0con high level when data > counter; low level when data < counter pnd interrupt enable/disable t0_ovf counter (t0cnt) interrupt enable/disable t0_int clk match pnd figure 10-8. simplified timer 0 function diagram: pwm mode
s3c9664/p9664 ( preliminary spec) basic timer and timer 0 10- 11 pwm function description the 8-bit counter counts modulus 256, that is, from 0?255, inclusive. the value of the 8-bit counter is compared to the contents of the reference registers, t0data. when the reference register value equals the counter value, the pwm output goes low. when the counter reaches zero, the pwm output is forced high. the low-to-high ratio (duty) of the pwm output is t0data/256. all pwm outputs remain inactive during the first 256 input clock signals. then, when the counter value changes from ffh back to 00h, the pwm outputs are forced to high level. the pulse width ratio (duty cycle) is defined by the contents of the reference register and is programmed in increments of 1:256. the 8-bit pwm data register t0data is read and written using 8-bit register addressing mode. pwm output can be held at low level by continuously loading the reference register with 00h. by continuously loading the reference register with ffh, you can hold the pwm output to high level, except for the last pulse of the clock source, which sends the output low (see figure 10-8). table 10-1. pwm reference register duty values reference register value (t0data) duty 0000 0000 0000 0001 0000 0010 ? ? 1000 0000 1000 0001 ? ? 1111 1110 1111 1111 0/256 (0 %) 1/256 (0.39 %) 2/256 (0.78%) ? ? 128/256 (50 %) 129/256 (50.4 %) ? ? 254/256 (99.2 %) 255/256 (99.6 %) 0 1 2 254 255 0 1 2 254 255 t0cnt value t0data = 00h t0data = 01h t0data = 80h t0data = ffh ... ~ ~ ... ~ ~ ... ~ ~ ... ~ ~ figure 10-9. pwm output waveforms
basic timer and timer 0 s3c9664/p9 664 ( preliminary spec) 10- 12 capture mode in capture mode, the timer 0 counter increases at a rate determined by the timer clock. the trigger signal (a rising or falling edge) for the capture operation occurs at the t0 pin. the interrupt service routine stores the captured 8 -bit timer 0 counter value in the timer 0 data register whenever the capture signal is detected at the t0 pin. by reading the counter value at programmed intervals, the routine can compare the differences between successive read values and calculate elapsed time interval. for example, if 80h is read and then 90h is read, this gives a difference of 10h. depending on the clock speed, you can convert this hexadecimal value into the equivalent time interval (in this case, it is approximately 10 milliseconds). pnd interrupt enable/disable t0_int t0con p0.0/t0 (cap) data register (t0data) t0_ovf interrupt enable/disable counter (t0cnt) clk pnd figure 10-10. simplified timer 0 function diagram: capture mode
s3c9664/p9664 ( preliminary spec) basic timer and timer 0 10- 13 mux mux div r 8-bit up-counter (t0cnt) 8-bit compatator timer 0 buffer register bits 5, 4 bit 0 bit 2 t0_int bit 3 clear data bus bit 0 t0_ovf 8-bit up counter (btcnt, read-only) div r x in x in ovf reset data bus clear when btcnt.4 is set after releasing from reset or stop mode, cpu clock starts. match basic timer control register (write '1010xxxxb' to disable.) note: during a power-on reset operation, the cpu is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter is set). bits 7, 6 bits 3, 2 bit 1 reset or stop (timer 0 overflow) bit3 (timer 0 match) t0 (pwm) basic timer control register timer 0 control register t0con (counter clear) match (interval timer mode) overflow data bus timer 0 data register (t0data) 1/4096 1/1 1/8 1/256 1/4096 1/1024 t0 (cap) bits 5, 4 r 1/128 1/1 timer 0 interrupt control register bit 1 figure 10-11. basic timer and timer 0 block diagram
s3c9664/p9664 ( preliminary spec) timer 1 11- 1 11 timer 1 overview the 8-bit timer 1 is an 8-bit general-purpose timer. timer 1 has the interval timer mode by using the appropriate t1con setting. timer 1 has the following functional components: ? clock frequency divider (f osc divided by 1024, 256, 64 or 8 ) with multiplexer ? 8-bit counter (t1cnt at address e2h, page 0), 8-bit comparator, and 8-bit reference data register (t1data at address eeh, page 0) ? timer 1 match interrupt generation ? timer 1 control register, t1con (at address e3h read/write, page 0) function description interval timer function the timer 1 module can generate an interrupt: the timer 1 match interrupt (t1_int). the application's service routine can detect a pending condition of t1_int by the software and execute it?s sub-routine. when this case is used, the t1_int pending bit must be cleared by the application sub-routine by writing a "0" to the t1con.0 pending bit. in interval timer mode, a match signal is generated when the counter value is identical to the value written to the t1 reference data register, t1data. the match signal generates a timer 1 match interrupt (ta_int) and clears the counter. if, for example, you write the value 10h to t1data and 0fh to t1con, the counter will increment until it reaches 10h. at this point, the timer 1 interrupt request is generated, the counter value is reset, and counting resumes. timer 1 control register (t1con) you use the timer 1 control register, t1con, to ? enable the timer 1 operating (interval timer) ? select the timer 1 input clock frequency ? clear the timer 1 counter, t1cnt ? enable the timer 1 interrupt ? clear timer 1 interrupt pending conditions
timer 1 s3c9664/p96 64 ( preliminary spec) 11- 2 t1con is located at address e3h, page 0, and is read/write addressable using register addressing mode. a reset clears t1con to '00h'. this sets timer 1 to disable interval timer mode, selects an input clock frequency of f osc /1024, and disables timer 1 interrupt. you can clear the timer 1 counter at any time during normal operation by writing a "1" to t1con.3. to enable the timer 1 interrupt , you must write t1con.2 and t1con.1 to "1". to generate the exact time interval, you should write t1con.3 and .0, which cleared counter and interrupt pending bit. to detect an interrupt pending condition, the application program polls pending bit, t1con.0. when a "1" is detected, a timer 0 interrupt is pending. when the t1_int sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 1 interrupt pending bit, t1con.0. timer 1 interrupt pending bit: 0 = no interrupt pending 0 = clear pending bit (when write) 1 = interrupt is pending .7 .6 .5 .4 .3 .2 .1 .0 lsb msb timer 1 control register (t1con) e3h, r/w, reset: 00h, page 0 timer 1 input clock selection bits: 00 = f osc /1024 01 = f osc /256 10 = f osc /64 11 = f osc /8 not used. timer 1 counter clear bit: 0 = no effect 1 = clear the timer 0 counter (when write) timer 1 interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer 1 count enable bit: 0 = disable counting operation 1 = enable counting operation figure 11-1. timer 1 control register (t1con)
s3c9664/p9664 ( preliminary spec) timer 1 11- 3 block diagram mux 8-bit up-counter (read-only) 8-bit compatator timer 1 buffer register t1_int clear data bus div x in match bits 7, 6 bit 2 8-bit counter is cleared by bit 3 data bus timer 1 data register (read/write) 1/1024 1/256 r 1/64 1/8 8 8 match bit 0 bit 3 bit 1 pending figure 11-2. timer 1 functional block diagram
s3c9664/p9664 ( preliminary spec) a/d converter 12- 1 1 2 a/d converter overview the a/d converter (adc) module uses successive approximation logic to convert analog levels at one of the six input channels to equivalent 10 -bit digital values. the analog input level must lie between the v dd and v ss values. the a/d converter has the following components: ? six multiplexed analog input pins (ad0?ad5) ? analog comparator with successive approximation logic ? 10-bit a/d conversion data output registers (addatah, addatal) ? adc control register (adcon) an analog-to-digital conversion procedure is initiated when the cpu writes a value to the adcon register at address (d8h, page 0) to select one of the six available input pins. you select the desired input channel by setting the appropriate bits in the adcon register. the s3c9664/p9664 microcontroller performs 10-bit conversions for only one input channel at a time. you can dynamically select different analog input channels during program execution by manipulating selection bits in the adcon register. during a normal conversion, adc logic initially sets the successive approximation register to 200h (the approximate half-way point of an 10-bit register). this register is then updated automatically during each conversion step. the successive approximation block performs 10-bit conversions for one input channel at a time. you can dynamically select different channels by mainpulating the channel selection bit value (adcon.6?4) in the adcon register. to start the a/d conversion, you should set a the enable bit, adcon.0. when a conversion is completed, acon.3, the end-of-conversion (eoc) bit is automatically set to 1 and the result is dumped into the addata register where it can be read. the a/d converter then enters an idle state. remember to read the contents of addata before another conversion starts. otherwise, the previous result will be overwritten by the next conversion result. note because the adc does not use sample-and-hold circuitry, it is important that any fluctuations in the analog level at the ad0?ad5 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to circuit noise, will invalidate the result.
a/d converter s3c9664/p9664 ( preliminary spec) 12- 2 internal reference voltage levels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must remain within the range av ss to v dd . different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first bit conversion is always 1/2 v dd . using a/d pins for standard digital input the adc module's input pins are alternatively used as digital input in port 1. the ad0?ad5 share pin names are p1.0?p1.5 a/d converter control register (adcon) the a/d converter control register, adcon, is located at address d8h, page 0. adcon has four functions: ? bits 6-4 select an analog input pin (ad0?ad51). ? bit 3 indicates the status of the a/d conversion. ? bit2-1 select clock source. ? bit 0 starts the a/d conversion. only one analog input channel can be selected at a time. you can dynamically select any one of the six analog input pins (ad0?ad5) by manipulating the 3-bit value for adcon.6?adcon.4 it?s recomanded that the clock source determinding the conversion speed would be less than 2.5 mhz to get sound results.
s3c9664/p9664 ( preliminary spec) a/d converter 12- 3 lsb msb a/d converter control registers d8h, r/w, page 0 conversion speed selection bit: (note) 00 = f osc /16 (f osc < 16 mhz) 01 = f osc /16 (f osc < 16 mhz) 10 = f osc /16 (f osc < 16 mhz) 11 = f osc /16 (f osc < 16 mhz) .7 .6 .5 .4 .3 .2 .1 .0 not used analog input pin selection bits: .6 0 0 0 0 1 1 1 1 .6 0 0 1 1 0 0 1 1 .6 0 1 0 1 0 1 0 1 selected input pin adc0 (p1.0) adc1 (p1.1) adc2 (p1.2) adc3 (p1.3) adc4 (p1.4) adc5 (p1.5) not used for ks86c6604 not used for ks86c6604 .3 0 1 end-of-conversion status bit: a/d conversion is in progress a/d conversion complete (when read) .0 0 1 conversion start bit: no effect a/d conversion start figure 12- 1. a/d converter control register (adcon)
a/d converter s3c9664/p9664 ( preliminary spec) 12- 4 a/d converter control register adcon (d8h, page 0) adcon .6-.4 + _ control circuit successive approximation circuit d/a converter v dd v ss addatal (d6h,page 0) addatah (d7h,page 0) adcon .0 (aden) adcon .3 (eoc flag) analog comparator conversion result to data bus multiplexer adc4/p1.4 adc0/p1.0 adc1/p1.1 adc2/p1.2 adc3/p1.3 adc5/p1.5 figure 1 2- 2. a/d converter circuit diagram .9 .8 .7 .6 .5 .4 .3 .2 lsb msb - - - - - - .1 .0 lsb msb addatah addatal figure 1 2-3 . a/d converter data register (addata)
s3c9664/p9664 ( preliminary spec) a/d converter 12- 5 50 adc clock 40 clock conversion start eoc addata previous value valid data 9 8 7 6 5 4 3 2 1 0 adcon.0 <-1 set up time 10 clock . . . addatah (8-bit) + addata (2-bit) figure 1 2-4 . a/d converter timing diagram conversion timing (s3c9664) the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up a/d conversion. therefore, total of 50 clocks are required to complete an 10-bit conversion: with an 10 mhz cpu clock frequency, one clock cycle is 400 ns (4/f osc ). if each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 10-bits + step-up time (10 clock) = 50 clocks 50 clock x 400 ns = 20 m s at 10 mhz, 1 clock time = 4/f osc (assuming adcon.2?.1 = 10) internal a/d conversion procedure 1. analog input must remain between the voltage range of v ss and av dd . 2. configure the analog input pins to input mode by making the appropriate settings in p1conh, p1conl 3. before the conversion operation starts, you must first select one of the eight input pins (ad0?ad5) by writing the appropriate value to the adcon register. 4. when conversion has been completed, (50 cpu clocks have elapsed), the eoc flag is set to "1", so that a check can be made to verify that the conversion was successful. 5. the converted digital value is loaded to the output register, addatah ( high 8-bit) and addatal (low 2- bit), then the adc module enters an idle state. the digital conversion result can now be read from the addatah and addata l registers.
s3c9664/p9664 (p reliminary s pec ) universal serial bus 13- 1 13 universal serial bu s overview universal serial bus (usb) is a communication architecture that supports data transfer between a host computer and a wide range of pc peripherals. usb is actually a cable bus in which the peripherals share its bandwidth through a host scheduled token based protocol. the usb module in s3c9664 is designed to serve at a low speed transfer rate (1.5 mbps) usb device as described in the universal serial bus specification revision 1.1. s3c9664 can be briefly described as a microcontroller with sam 87rcri core with an on-chip usb peripheral as can be seen in figure 13-1. the s3c9664 comes equipped with serial interface engine (sie), which handles the communication protocol of the usb. the s3c9664 supports the following control logic: packet decoding/generation, crc generation/checking, nrzi encoding/decoding, sync detection, eop (end of packet) detection and bit stuffing. s3c9664 supports two types of data transfer; control and interrupt. three endpoints are used in this device; endpoint 0, endpoint 1, endpoint2. please refer to the usb specification revision 1.1 for detail description of usb. sam88rcri core data bus transceiver voltage regulator sie (serial interface engine) d+ d- endpoint 0 fifo endpoint 1 fifo endpoint 2 fifo figure 13-1. usb peripheral interface
universal serial bus s3c9664/p9664 (p reliminary s pec ) 13- 2 serial bus interface engine (sie) the serial interface engine interfaces to the usb serial data and handles, deserialization/serialization of data, nrzi encoding/decoding, clock extraction, crc generation and checking, bit stuffing and other specifications pertaining to the usb protocol such as handling inter packet time out and pid decoding. control logic the usb control logic manages data movements between the cpu and the transceiver by manipulating the transceiver and the endpoint register. this includes both transmit and receive operations on the usb. the logic contains byte count buffers for transmit operations that load the active transmit endpoint's byte count and use this to determine the number of bytes to transfer. the same buffer is used for receive transactions to count the number of bytes received and transfer that number to the receiver endpoint's byte count register at the end of the transaction. the control logic in s3c9664, when transmit, manages parallel to serial conversion, packet generation, crc generation, nrzi encoding and bit stuffing. when receive, the control logic in s3c9664 handles sync detection, packet decoding, eop (end of packet) detection, remove bit stuffing, nrzi decoding, crc checking and serial to parallel conversion bus protocol all bus transactions involve the transmission of packets. s3c9664 supports low-speed packets. each transaction starts when the host controller sends a token packet to the usb device. the token packets are generated by the usb host and decoded by the usb device. a token packet includes the type description, direction of the transaction, usb device address and the endpoint number. data and handshake packets are both decoded and generated by the usb device. in any transaction, the data is transferred from the host to a device or from a device to the host. the transaction source then sends a data packet or indicates that it has no data to transfer. the destination then responds with a handshake packet indicating whether the transfer was successful. data transfer types usb data transfer occurs between the host software and a specific endpoint on the usb device. an endpoint supports a specific type of data transfer. the s3c9664 supports two types transfer endpoints: control and interrupt. control transfer configures and assigns an address to the device when detected. control transfer also supports status transaction, returning status information from device to host. interrupt transfer refers to a small, spontaneous data transfer from usb device to host. endpoints communication flows between the host software and the endpoints on the usb device. each endpoint on a device has an identifier number. in addition to the endpoint number, each endpoint supports a specific transfer type. s3c9664 supports three endpoints: endpoint 0 supports control transfer, and endpoint 1, endpoint 2 supports interrupt transfer.
s3c9664/p9664 (p reliminary s pec ) universal serial bus 13- 3 enable reference voltage generator 3.3 v current amplifier a b note: this block can give a explanation how it can be controlled automatically. when the 3.3 voltage regulator be enable by software, voltage regulator will operating to cover fluctuation of the line load, sometimes the line is not stabled and the driving ability will be dropped. as it operating in the normal stage without any peak, power will be supplied with 8 ma, and when the operating. current consumption go to peak, it was designed to cover by 50 ma. it meas any kind of load problem will be compensated with above design. figure 13-2. block diagram of voltage regulator
universal serial bus s3c9664/p9664 (p reliminary s pec ) 13- 4 ctrl d- d+ slope control a b v33in control sinals enable dm tx/rx dp tx/rx c d dm dp pull-up control r, 1.5 k w 5 % + note: we didn't used the by-pass capacitor on the 3.3 v out, since the 3.3 v regulator and clamp circuit will give a solution through the feedback. usb block was designed to cover the line load, the typical value designed is 300 pf (max: 800 pf). the calmp block operating after it detect the voltage variation (actually the current fluctuation will be feedback into voltage variation, di/dt to dt/dt variation. bias control the slope. control signals means nrzi, eop, xcon, in/out. enable is for the tx, rx. internal pull-up resistor will be 1.5 k w 10 % + figure 13-3. block diagram of usb signal transceiver v dd dm_drvp dm_drvn dm gpio pull-up enable v dd dp_drvp dp_drvn dp gpio pull-up enable note: it explain the ps2 block. the pull-up resistor value will be 4.3 k w 20 % this block can be controlled with pull-up resistor and it was designed with totally different from usb. + figure 13-4. block diagram of gpio signal transmitter
s3c9664/p9664 (p reliminary s pec ) universal serial bus 13- 5 usb function address register (faddr) this register holds the usb address assigned by the host computer. faddr is located at address f0h, page 0 and is read/write addressable. bit7 not used (read value will be always "0"). bit6?0 faddr: mcu updates this register when it decodes a set_address command. mcu must write this register with clears out_pkt_rdy (bit0) and sets data_end (bit3) in the ep0csr register. that is, mcu should write #48h to ep0csr register after write this register. the function controller use this register's value to decode usb token packet address. reset value of this register is ?0?. the new address will work after successful status stage. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb usb function address register (faddr) f0h, r/w, page 0 7-bit programming device address. this register maintains the usb address assigned by the host. the function controller uses this register's value to decode usb token packet address. at reset when the device is not yet configured the value is reset to 0. not used figure 13-5. usb function address register (faddr)
universal serial bus s3c9664/p9664 (p reliminary s pec ) 13- 6 control endpoint status register (ep0csr) ep0csr register controls endpoint 0 (control endpoint), and also holds status bits for endpoint 0. ep0csr is located at f1h and is read/write addressable. bit7 clear_setup_end : mcu writes ?1? to this bit to clear setup_end bit (bit4). this bit is automatically cleared after clearing setup_end bit by sie. so read value will be always ?0?. bit6 clear_out_pkt_rdy: mcu writes ?1? to this bit to clear out_pkt_rdy bit (bit0). this bit is automatically cleared after clearing out_pkt_rdy bit by usb block. so read value will be always ?0?. bit5 send_stall: mcu writes ?1? to this bit to send stall packet to host, it must clear out_pkt_rdy (bit 0) at the same time. if mcu receive invalid command then should write #60h to this register. the sie issues a stall handshake to the current control transfer(means next transaction). this bit will be cleared after sending stall handshake. bit4 setup_end : sie sets this bit, when a control transfer ends without setting data_end bit (bit3). mcu clears this bit, by writing a ?1? to clear_setup_end bit (bit7). when sie sets this bit, an interrupt is generated to mcu. when such condition occurs, sie flushes the fifo. mcu can not access to fifo until this bit cleared. this flag is a read only bit so mcu can not write to this bit directly. bit3 data_end: mcu sets this bit: ? after loading the last packet of data into the fifo, and at the same time in_pkt_rdy bit should be set. ? while it clears out_pkt_rdy bit after unloading the last packet of data. ? for a zero length data phase, this bit should be set when it clears out_pkt_rdy bit. bit2 sent_stall: sie sets this bit after send stall handshake to host. there are two cases which issue stall packet to host. if mcu set send_stall bit, then sie will send stall to the next transaction and set this bit. the other case is send stall by sie automatically since protocol violation. an interrupt is generated when this bit gets set. this bit is a read/write bit so mcu should clears this bit to end the stall condition. bit1 in_pkt_rdy: mcu sets this bit, after loading data into endpoint 0 fifo. sie clears this bit, once the packet has been successfully sent to the host. an interrupt is generated when sie clears this bit so that mcu can load the next packet. for a zero length data phase, mcu sets in_pkt_rdy bit without load data to fifo. bit0 out_pkt_rdy: sie sets this bit, if the device receive valid data from host. an interrupt is generated, when sie sets this bit. mcu should download data and clears this bit by writing "1? to clear_out_pkt_rdy bit at the end of execution. notes: 1. when setup_end bit is set, out_pkt_rdy bit may also be set. this happens when the current tr ansfer has terminated by new setup transaction. in such case, mcu should first clear setup_end bit, and then start servicing the new control transfer.
s3c9664/p9664 (p reliminary s pec ) universal serial bus 13- 7 intrrupt endpoints status register (ep1csr, ep2csr) ep1csr register controls endpoint 1, and also holds status bits for endpoint 1. ep1csr is located at f2h and is read/write addressable. ep2csr register controls endpoint2, and the contents is perfectly same to ep1csr. ep2csr is located at f9h and is read/write addressable. ep1csr and ep2csr have two modes. these are in and out mode which are decided by endpoint_mode register. the below is in mode configuration. bit7 clr_data_toggle : mcu write "1" to this bit for initializing data toggle sequence. data toggle sequence can be monitored through wrt_cnt register. bit6 maxp[3]. bit5 maxp[2]. bit4 maxp[1]. bit3 maxp[0]. ? ks86p6604 is a low speed usb controller so the maximum packet size is 8 bytes, ? this part is a limitation of maxmum packet size so the device can not send more data than this value. bit2 uc_fifo_flush : mcu sets this bit for initializing the fifo. mcu can not clear in_pkt_rdy so if mcu want to clear in_pkt_rdy after set then mcu should issue uc_fifo_flush for clearing in_pkt_rdy. bit1 force_stall : mcu sets this bit for sending stall packet. this flag will not be cleared by sie. so mcu should clear this flag for stopping stall condition. device will send stall until this flag is cleared. bit0 in_pkt_rdy : mcu sets this bit after loading data to fifo. sie will clear this flag after sending data to host. an interrupt is generated when this flag is cleared. if mcu issue uc_fifo_flush during this flag set then this flag is cleared and generate interrupt to mcu. so mcu will get interrupt directly after setting uc_fifo_flush flag if this flag was set.
universal serial bus s3c9664/p9664 (p reliminary s pec ) 13- 8 intrrupt endpoints status register (ep1csr, ep2csr) the below is out mode configuration. bit7 reserved . bit6 clear_out_pkt_rdy : mcu writes "1" to this bit to clear out_pkt_rdy bit (bit0). this bit is automatically cleared after clearing out_pkt_rdy bit by sie. so read value will be always "0". bit5 reserved . bit4 reserved . bit3 sent_stall : . this flag is set by sie after sending stall packet. and this flag is just for monitoring the action of sie so it does not mean any other things. this flag can be cleared by mcu. bit2 uc_fifo_flush : mcu sets this bit for initializing the fifo. mcu can not clear in_pkt_rdy so if mcu want to clear in_pkt_rdy after set then mcu should issue uc_fifo_flush for clearing in_pkt_rdy. bit1 force_stall : mcu sets this bit for sending stall packet. this flag will not be cleared by sie. so mcu should clear this flag for stopping stall condition. device will send stall until this flag is cleared. bit0 out_pkt_rdy : sie sets this bit, if the device receive valid data from host. an interrupt is generated, when sie sets this bit. mcu should download data and clears this bit by writing "1" to clear_out_pkt_rdy bit at the end of execution.
s3c9664/p9664 (p reliminary s pec ) universal serial bus 13- 9 endpoint 0 write count register (ep0bcnt) ep0bcnt register contains data count value, some monitoring and flow control flag. ep0bcnt is located at f3h, page 0 and read addressable. bit7 data_toggle : this bit is a read only flag. this flag is just for monitoring the data toggle sequence. bit6 token : .this flag is for monitoring. if this value is set then it means the last received token packet is setup token and if the value is ?0? then the last received token packet is out or in packet. bit5 over_8 : .if device receive over 8 bytes setup or out transaction then the device does not answer to these transaction and set this flag as a error indicator. bit4 enable : . mcu set this bit for disabling endpoint 0. device does not answer to any traffic if addressed to endpoint 0 until this bit is cleared. bit3 ep0wrt_cnt[3] . bit2 ep0wrt_cnt[2] . bit1 ep0wrt_cnt[1] . bit0 ep0wrt_cnt[0] : sie store data count after receive valid data from host. the maximum value is 8. and if mcu downloading the fifo then this value also decreased according to remain data count.
universal serial bus s3c9664/p9664 (p reliminary s pec ) 13- 10 endpoint 1 write count register (ep1bcnt) ep1bcnt register contains data count value, some monitoring and flow control flag. ep1bcnt is located at fch, page 0 and read/write addressable. bit7 data_toggle : this bit is a read only flag. this flag is just for monitoring the data toggle sequence. bit6 reserved. bit5 over_8 : .if device receive over 8 bytes setup or out transaction then the device does not answer to these transaction and set this flag as a error indicator. bit4 enable : . mcu set this bit for disabling endpoint 1. device does not answer to any traffic if addressed to endpoint 1 until this bit is cleared. bit3 ep1wrt_cnt[3] . bit2 ep1wrt_cnt[2] . bit1 ep1wrt_cnt[1] . bit0 ep1wrt_cnt[0] : sie store data count after receive valid data from host. the maximum value is 8. and if mcu downloading the fifo then this value also decreased according to remain data count.
s3c9664/p9664 (p reliminary s pec ) universal serial bus 13- 11 endpoint 2 write count register (ep2bcnt) ep2bcnt register contains data count value, some monitoring and flow control flag. ep2bcnt is located at fdh, page 0 and read/write addressable. bit7 data_toggle : this bit is a read only flag. this flag is just for monitoring the data toggle sequence. bit6 reserved. bit5 over_8 : .if device receive over 8 bytes setup or out transaction then the device does not answer to these transaction and set this flag as a error indicator. bit4 enable : . mcu set this bit for disabling endpoint 2. device does not answer to any traffic if addressed to endpoint 2 until this bit is cleared. bit3 ep2wrt_cnt[3] . bit2 ep2wrt_cnt[2] . bit1 ep2wrt_cnt[1] . bit0 ep2wrt_cnt[0] : sie store data count after receive valid data from host. the maximum value is 8. and if mcu downloading the fifo then this value also decreased according to remain data count.
universal serial bus s3c9664/p9664 (p reliminary s pec ) 13- 12 endpoint mode register (epmode) epmode register contains the field which defines usb reset signal length and the field which defines the direction of endpoints. epmode is located at fbh, page 0 and read/write addressable. bit7 reset_length[1] . bit6 reset_length[0] : this field defines the length of usb reset signal. the reset value is "00". mcu can control usb reset length through this field. the definition is as below. ? "00" : 22.4 m s + a ? "01" : 12.0 m s + a ? "10" : 6.0 m s + a . ? "11" : 4.0 m s + a ( a @ 0.66 m s) bit5 reserved. bit4 reserved. bit3 reserved. bit2 reserved. bit1 endpoint_mode[1] : mcu can defines direction of interrupt transfer. if this value is "1" then endpoint 2 act as a out interrupt endpoint and if this value is "0" then endpoint 2 act as a in interrupt endpoint. the reset value is ?0?. bit0 endpoint_mode[0] : mcu can defines direction of interrupt transfer. if this value is "1" then endpoint 1 act as a out interrupt endpoint and if this value is "0" then endpoint 1 act as a in interrupt endpoint. the reset value is ?0?.
s3c9664/p9664 (p reliminary s pec ) universal serial bus 13- 13 usb power management register (pwrmgr) pwrmgr register interacts with the host's power management system to execute system power events such as suspend or resume. and this register also contains monitoring field for detail control of mcu. this register is located at address f8h, page 0 and is read/write addressable. bit7 reserved . bit6 reserved . bit5 reserved . bit4 vpin : mcu can read the vpin value through this bit. this value is the output of transceiver and the input of usb module. and this value is different from the port vpin value. port vp value is the input of controller, not usb module. bit3 vmin : mcu can read the vmin value through this bit. this value is the output of transceiver and the input of usb module. and this value is different from the port vmin. port vm value is the input of controller, not usb module. bit2 clear_susp_cnt : mcu write "1" value to this bit for clearing suspend counter which count 3 ms. and during this value stay "1" the suspend counter does not proceed. that means the usb controller can not go into suspend state during this value stays "1". bit1 send_resume: while in suspend state, if the mcu wants to initiate resume, it writes "1" to this register for 10ms (maximum of 15ms), and clears this register. in suspend mode if this bit reads "1" then sie generates resume signaling to upstream. bit0 suspend_state: suspend state is set when the mcu sets suspend interrupt. this bit is cleared automatically when: ? mcu writes "0" to send_resume bit to end the resume signaling (after send_resume is set for 10ms). ? mcu receives resume signaling from the host while in suspend mode. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb usb power mangement register (pwrmgr) f8h, r/w suspend_state reserved send_resume clear_susp_cnt vmin vpin figure 13-6. usb power management register (pwrmgr)
universal serial bus s3c9664/p9664 (p reliminary s pec ) 13- 14 control endpoint fifo register (ep0fifo) this register is bi-directional, 8 byte depth fifo used to transfer control endpoint data. ep0fifo is located at address f4h and is read/write addressable. initially, the direction of the fifo, is from the host to the mcu. after a setup token is received for a control transfer, that is, after mcu unload the setup token bytes, and clears out_pkt_rdy, the direction of fifo is changed automatically from mcu to the host. interrupt endpoint 1 fifo register (ep1fifo) ep1fifo is an bi-direction 8-byte depth fifo used to transfer data from the mcu to the host or from the host to the mcu. mcu writes data to this register, and when finished set in_pkt_rdy. meanwhile, when usb recieves valid data through this register , it sets out_pkt_rdy , after mcu unload data bytes, and clears out_pkt_rdy , this register is located at address f5h. interrupt endpoint 2 fifo register (ep2fifo) ep2fifo is an bi-direction 8-byte depth fifo used to transfer data from the mcu to the host or from the host to the mcu. mcu writes data to this register, and when finished set in_pkt_rdy. meanwhile, when usb recieves valid data through this register , it sets out_pkt_rdy , after mcu unload data bytes, and clears out_pkt_rdy , this register is located at address fah. usb interrupt pending register (usbpnd) usbpnd register has the interrupt bits for endpoints and power management. this register is cleared once read by mcu. while any one of the bits is set, an interrupt is generated. usbpnd is located at address f6h. bit7?6 not used bit5 usb_rst_pnd: this bit is set, when usb reset signal is received. bit4 endpt2_pnd: this bit is set, when endpoint 2 needs to be received. bit3 resume_pnd: while in suspend mode, if resume signaling is received this bit gets set. bit2 suspend_pnd: this bit is set, when suspend signaling is received. bit1 endpt1_pnd: this bit is set, when en dpoint 1 needs to be serviced. bit0 endpt0_pnd: this bit is set, when endpoint 0 needs to be serviced. it is set under any one of the following conditions: ? out_pkt_rdy is set. ? in_pkt_rdy gets cleared. ? sent_stall gets set. ? data_end gets cleared. ? setup_end gets set.
s3c9664/p9664 (p reliminary s pec ) universal serial bus 13- 15 .7 .6 .5 .4 .3 .2 .1 .0 lsb msb usb interrupt pending register (usbpnd) f6h, r/w, page 0 suspend_pnd endpt1_pnd endpt0_pnd not used resume_pnd usb_rst_pnd endtt2_pnd figure 13-7. usb interrupt pending register (usbpnd)
universal serial bus s3c9664/p9664 (p reliminary s pec ) 13- 16 usb interrupt enable register (usbint) usbint is located at address f7h, page 0 and is read/write addressable. this register serves as an interrupt mask register. if the corresponding bit = 1 then the respective interrupt is enabled. by default, all interrupts except suspend interrupt is enabled. interrupt enables bits for suspend and resume is combined into a single bit (bit 2). bit7?5 not used bit4 enable_usb_rst_int: 1 enable usb reset interrupt (default) 0 disable usb reset interrupt bit3 enable_endpt2_int: 1 enable endpoint 2 interrupt (default) 0 disable endpoint 2 interrupt bit2 enable_suspend_resume_int: 1 enable suspend and resume interrupt 0 disable suspend and resume interrupt (default) bit1 enable_endpt1_int: 1 enable endpoint 1 interrupt (default) 0 disable endpoint 1 interrupt bit0 enable_endpt0_int: 1 enable endpoint 0 interrupt (default) 0 disable endpoint 0 interrupt .7 .6 .5 .4 .3 .2 .1 .0 lsb msb usb interrupt enable register (usbint) f7h, r/w, page 0 enable_endpt0_int not used enable_endpt1_int enable_suspend_resume_int enable_zndpt2_int enable_usb_rst_int figure 13-8. usb interrupt enable register (usbint)
s3c9664/p9664 (p reliminary s pec ) universal serial bus 13- 17 usb control register (usbcon) usbcon is for the control of usb data line and the control of reset .this register is located at address feh, page 0 and is read/write addressable. bit5 dp/dm control: when this bit is set , dp/dm lines can be controlled by mcu as bellows bit4 dp: on the condition of bit5 set, if this bit is 1 , dp line is to be high and the other case this bit is 0 dp line is low . bit3 dm: on the condition of bit5 set, if this bit is 1 , dm line is to be high and the other case this bit is 0 dm line is low . bit2 usb_reset_en: when this bit is set , it is usb is made reset , which trigger mcu reset automatically bit1 mcu_reset: when this bit is set , mcu makes usb reset bit1 usb_rstn: usb reset status bit 0 : usb is not reset 1 : usb is reset .7 .6 .5 .4 .3 .2 .1 .0 lsb msb usb control register (usbcon) feh (page 0), r/w usb_rstn not used mcu_reset usb_reset_en dp/dm_control dp dm figure 13-9. usb control register (usbcon)
universal serial bus s3c9664/p9664 (p reliminary s pec ) 13- 18 xcon register (xcon) xcon register is an 8-bit register that is used to adjust signal quality and port2 (d+/d-) configuration. this register is located at address feh (page1 ) and is read/write addressable. bit7 pull-up resister at(d-) enable bit: 0 : pull up resister at (d-) disable 1 : pu ll up resister at (d-) enable bit7 gpio or usb port select bit: 0 : general in/out port enable 1 : usb port enable note: dly means delay time of rising/fallling time. num hex value 1 2 3 4 5 0x00 0x38 0x3c 0x3d 0x3e result, dm default value, 0.88 v, 1.19 v 1.58 v, 1.55 v 1.50 v, 1.50 v 1.65 v, 1.65 v 1.80 v, 1.80 v good note: this value is only for otp products. edge control bit 5, 2 bit 4, 1 bit 3, 0 dly value unit about 2.5 nsec 0 0 1 0 1 1 0 1 dly 0 dly 1 dly 2 dly 4 0 rise edge 1 1 1 0 0 0 0 1 dly 4 dly 2 dly 1 dly 0 1 fall edge x x x x 5 4 3 2 1 0 bit dm dp (v dd = 5.12 v) x - point 1 x - point 2 dp dm dp
s3c9664/p9664 (p reliminary s pec ) sub rc oscillator 14- 1 1 4 sub rc oscillator overview the s3c9664 have a programmable sub rc oscillator. during idle or stop, programmable sub rc oscillator generated interrupt using sub rc oscillator control register (subcon). sub rc oscillator control register (subcon) .7 .6 .5 .4 .3 .2 .1 .0 lsb msb sub rc oscillator control register interrupt enable bit: 1 = interrupt enable 0 = interrupt disable interrupt pending bit: 1 = no pending 0 = pending sub rc oscillator counter input clock selection bits: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 f osc /2048 f osc /3072 f osc /4096 f osc /6144 f osc /8192 f osc /12288 f osc /16384 f osc /24576 sub rc oscillator enable bit: 1 = sub oscillator enable 0 = sub oscillator disable not used note: f osc = 130 khz typ. when v dd = 0.5 v, t a = 25 c figure 14-1. sub rc oscillator control register
s3c9664/p9664 (preliminary spec) lvr (low voltage reset reset ) 15- 1 1 5 lvr (low voltage reset reset ) overview the s3c9664 have a lvr (low voltage reset) for power on reset and voltage reset. comparator glitch filter reset reference voltage generator voltage divider start up figure 15-1. lvr architecture ? low voltage reset generated reset signal. ? start up circuit: start up referen ce voltage generator circuit when device powered. ? reference voltage generator: supply voltage independent reference voltage generator. ? voltage divider: divide supply voltage by ?n? ? comparator: compare reference voltage and divided voltage. ? glitch filter: remove glitch and noise signal.
lvr (low voltage reset reset ) s3c9664/p9664 (preliminary spec) 15- 2 vc (compare voltage) reference voltage divide voltage v dd (supply voltage) normal operation reset operation by lvd notes: 1. lvd operation voltage range: 2.3 v-6.0 v 2. lvd detection voltage range: 3.4 v 0.4 v 3. lvd current consumption: less then 10 ua (normally 5 ua) 4. lvd powered reset release time: more then 500 usec (lvd only, typical) 5. lvd simulation conditions (hspice simulation) temp: 0 - 80 c process veriation: worst to best conditions test voltage: 0.0 v-7.0 v powered slew rate: 5 v/1 usec- 5 v/10 msec figure 15-2. lvr characteristics
s3c9664/p9664 (preliminary spec) lvr (low voltage reset reset ) 15- 3 lvr and power on reset reset operations normal operating mode t wait = (4096x16)/f osc basic timer increment and cpu operations are idle mode 10000b 00000b notes: 1. t1 = 500 usc (at normal) 2. t2 = t1 + (4096 x 16)/f osc v dd lvd reset release internal reset release oscillator (x out ) btcnt clock btcnt value oscillator stabilization time t3 oscillation stabilization time t2 t1 lvd reset release time figure 15-3. lvr and power on reset reset operation
s3c9664/p9664 (p reliminary s pec ) electrical data 1 6- 1 1 6 electrical data overview in this section, the following s3c9664 electrical characteristics are presented in tables and graphs: ? absolute maximum ratings ? d.c. electrical characteristics ? i/o capaci tance ? a.c. electrical characteristics ? oscillator characteristics ? operating voltage range ? oscillation stabilization time ? clock timing measurement points at x in ? data retention supply voltage in stop mode ? stop mode release timing when initiated by a reset ? stop mode release timing when initiated by an external interrupt ? characteristic curves ? ad converter electrical characteristics
electrical data s3c9664/p9664 (p reliminary s pec ) 1 6- 2 table 16- 1 . absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all ports ? 0.3 to v dd + 0.3 v output voltage v o all o utput ports ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 18 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 ma total pin current for ports 0, 1 , 2 + 100 operating temperature t a ? 0 to + 85 c storage temperature t stg ? ? 60 to + 150
s3c9664/p9664 (p reliminary s pec ) electrical data 1 6- 3 table 16- 2 . d.c. electrical characteristics (t a = ? 4 0 c to + 85 c, v dd = 4. 0 v to 5.25 v) parameter symbol conditions min typ max unit input highvoltage v ih1 all input pins except v ih2, d+, d? 0.8 v dd ? v dd v v ih2 x in v dd ? 0.5 v dd input low voltage v il1 all input pins except v il2, d+, d? ? ? 0.2 v dd v il2 x in ? ? 0.4 output high voltage v oh v dd = 4.0 v ? 5.25 v i oh = ? 200 ma all output ports except d+, d? v dd ? 1.0 ? ? output low voltage v ol v dd = 4.0 v ? 5.25 v i ol = 2 ma all output ports except d+, d? ? ? 0.4 input high leakage current i lih1 v in = v dd all inputs except i lih2 except d+, d?, x out ? ? 3 a i lih2 v in = v dd, x in ? ? 20 input low leakage current i lil1 v in = 0 v all inputs except i lil2 except d+, d?, x out ? ? ? 3 i lil2 v in = 0 v, x in ? ? ? 20 output high leakage current i loh v out = v dd all output pins except d+, d? ? ? 3 output low leakage current i lol v out = 0 v all output pins except d+, d? x out ? ? ? 3 pull-up resistors r l1 v in = 0 v, v dd = 5.0 v, port 0, port 1,port2 25 50 100 k w r l2 v in = 0 v, v dd = 5.0 v, reset only 100 220 400 pull-down resistors r l3 v in = 0 v, v dd = 5.0 v, port 0 25 50 100 k w supply current i dd1 normal operation mode, v dd = 5 v 10 %, 6 mhz, cpu clock ? 6.5 15 ma i dd2 idle mode v dd = 5 v 10 %, 6 mhz, cpu clock ? 4 8 i dd3 stop mode, oscillator stop v dd = 5 v 10 %, ? 150 300 a notes : 1. supply current does not include current drawn through internal pull-up resistors or external output current load. 2. this parameter is guaranteed, but not tested (include d+, d?). 3. only in 4.0 v to 5.25 v, d+ and d? satisfy the usb spec 1.1.
electrical data s3c9664/p9664 (p reliminary s pec ) 1 6- 4 table 16- 3 . input/output capacitance (t a = 0 c to + 85 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io expect x in , x out xi/xo capacitance c xi , c xo x in , x out 33 table 16- 4 . a.c. electrical characteristics (t a = ? 4 0 c to + 85 c, v dd = 4. 0 v to 5.25 v) parameter symbol conditions min typ max unit noise filter t nf1h , t nf1l p 1 (rc delay) 100 ? 200 ns 0.8 v dd 0.2 v dd t nf1l t nf1h 0.5 v dd t nf2 figure 16-1. input timing for external interrupts
s3c9664/p9664 (p reliminary s pec ) electrical data 1 6- 5 table 16-5. oscillator characteristics (t a = 0 c + 85 c) oscillator clock circuit test condition min typ max unit main crystal main ceramic (f osc ) x in x out oscillation frequency v dd = 4.0 v ? 5.25 v ? 6.0 ? mhz external clock x in x out oscillation frequency v dd = 4.0 v ? 5.25 v ? 6.0 ? table 16- 6 . oscillation stabilization time (t a = 0 c + 85 c, v dd = 4. 0 v to 5.25 v) oscillator test condition min typ max unit main crystal v dd = 4. 0 v to 5.25 v , f osc > 6.0 mhz ? ? 10 ms main ceramic (oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range.) oscillator stabilization wait time t wait stop mode release time by a reset ? 2 1 6 /f osc ? t wait stop mode release time by an interrupt ? ? ? note : the oscillator stabilization wait time, t wait , when it is released by an interrupt, is determined by the setting in the basic timer control register, btcon.
electrical data s3c9664/p9664 (p reliminary s pec ) 1 6- 6 0.4 v t xl t xh x in 1/f osc v dd - 0.5 v figure 16-2. clock timing measurement points at x in table 16- 7 . data retention supply voltage in stop mode (t a = 0 c to + 70 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2.0 ? 6 v data retention supply current i dddr stop mode; v dddr = 2.0 v ? ? 5 a
s3c9664/p9664 (p reliminary s pec ) electrical data 1 6- 7 data retention mode ~ ~ ~ v dddr execution of stop instrction v dd normal operating mode idle mode (basic timer active) ~ stop mode t wait 0.8 v dd 0.2 v dd external interrupt figure 16-3. stop mode release timing when initiated by an external interrupt table 16-8. low speed source electrical characteristics (usb) (t a = 0 c to + 85 c, voltage regulator output v 33out = 2.8 v to 3.5 v, typ 3,3 v) parameter symbol conditions min max unit transition time: rise time tr cl = 200 pf 75 ? ns cl = 650 pf ? 300 fall time tf cl = 200 pf 75 ? cl = 650 pf ? 300 rise/fall time matching trfm ( tr/ tf) cl = 50 pf 80 125 % output signal crossover voltage vcrs cl = 50 pf 1.3 2.0 v output voltage regulator built-in v 33out v dd = 4.0 ?5.25 v 2.8 3.6 v
electrical data s3c9664/p9664 (p reliminary s pec ) 1 6- 8 r1 = 15 k w r2 = 1.5 k w cl = 200 pf - 650 pf dm: s/w on dp: s/w off d. u. t test point s/w v 33out r2 r1 c2 90 % measurement points 10 % 90 % 10 % tr tf figure 16-4. usb data signal rise and fall time dm dp v crs max: 2.0 v min: 1.3 v 3.3 v 0 v figure 16-5. usb output signal crossover point voltage
s3c9664/p9664 (p reliminary s pec ) electrical data 1 6- 9 table 16-9. a/d converter electrical characteristics (t a = ? 40 c to + 85 c, v dd = 4.2 v to 5.25 v, v ss = 0 v) s3c9664/p9664: 10-bit adc parameter symbol test conditions min typ max unit total accuracy v dd = 5.12 v cpu clock = 10 mhz v dd = 5.12 v v ss = 0 v ? ? 3 lsb integral linearity error ile ? ? 2 differential linearity error dle ? ? 1 offset error of top eot ? ? 1 3 offset error of bottom eob ? ? 1 2 conversion time (1) t con fcpu = 10 mhz ? 50x4/ f osc ? m s analog input voltage v ian ? v ss ? v dd v analog input impedance r an ? 2 ? ? m w analog input current i adin v dd = 5 v ? ? 10 m a adc block i adc v dd = 5 v ? 1 3 ma current (2) v dd = 5 v power down mode ? 100 500 na notes: 1. ?conversion time? is the time required from the moment a conversion operation starts until it ends. 2. i adc is operating current during a/d conversion.
s3c9664/p9664 (p reliminary s pec ) mechanical data 1 7- 1 17 mechanical data overview this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram note : dimensions are in millimeters. 26.80 max 26.40 0 .20 (1.77) 20-dip-300a 6.40 0 .20 #20 #1 0.46 0.10 1.52 0.10 #11 #10 0-15 0.25 + 0.10 - 0.05 7.62 2.54 0.51 min 3.30 0.30 3.25 0.20 5.08 max figure 17-1. 20-dip-300a package dimensions
mechanical data s3c9664/p9664 (p reliminary s pec ) 1 7- 2 note : dimensions are in millimeters. 20-sop-300 7.80 0 .30 #11 #20 #1 #10 14.10 max 13.70 0 .20 (1.14) 0-8 0.20 + 0.10 - 0.05 7.62 5.40 0.20 0.64 0.20 0.05 min 1.70 0.10 2.00 max 0.40 0.10 max + 0.10 - 0.05 1.27 figure 1 7- 2 . 20-sop-300 package dimensions
s3c9664/p9664 (p reliminary s pec ) mechanical data 1 7- 3 note : dimensions are in millimeters. 23.35 max 22.95 0 .20 (1.70) 24-sdip-300 6.40 0 .20 #24 #1 0.46 0.10 0.89 0.10 #13 #12 0-15 0.25 + 0.10 - 0.05 7.62 3.25 0.20 5.08 max 1.778 0.51 min 3.30 0.30 figure 17-3. 24-sdip-300 package dimensions
mechanical data s3c9664/p9664 (p reliminary s pec ) 1 7- 4 note : dimensions are in millimeters. 24-sop-300 7.90 0 .30 #13 #24 #1 #12 15.60 max 15.20 0 .20 0-8 0.20 + 0.10 - 0.05 7.62 5.30 0.20 0.60 0.20 0.05 min 1.75 0.10 2.00 max 0.45 0.10 max + 0.10 - 0.05 1.27 figure 17-4. 24-sop-300 package dimensions
s3c9664/p9664 (p reliminary s pec ) S3P9664 otp 18- 1 18 S3P9664 otp overview the s3c9664 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c9664 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the S3P9664 is fully compatible with the s3c9664, both in function and in pin configuration. because of its simple programming requirements, the S3P9664 is ideal for use as an evaluation chip for the s3c9664. v ss /v ss x out x in test /test p0.0/int0/t0 (cap/pwm) p0.1/int0 reset reset /reset p0.2/int0 p0.3/int0 p0.4/int0 S3P9664 (20-sop-300) (20-dip-300) 1 2 3 4 5 6 7 8 9 10 v dd / v dd d-/p2.0/int2/ sclk d+/p2.1/int2/ sdat p1.0/ad0/int1 p1.1/ad1/int1 p1.2/ad2/int1 p1.3/ad3/int1 p1.4/ad4/int1 p1.5/ad5/int1 p0.5/int0 20 19 18 17 16 15 14 13 12 11 figure 18-1. S3P9664 pin assignments (20-pin package)
S3P9664 otp s3c9664/p9664 (p reliminary s pec ) 18- 2 v ss /v ss x out x in test /test p0.0/int0/t0 (cap/pwm) p0.1/int0 reset reset /reset p0.2/int0 p0.3/int0 p0.4/int0 p0.6/int0 p0.7/int0 S3P9664 (24-sop-300) (24-sdip-300) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v dd / v dd d-/p2.0/int2/ sclk d+/p2.1/int2/ sdat p1.0/ad0/int1 p1.1/ad1/int1 p1.2/ad2/int1 p1.3/ad3/int1 p1.4/ad4/int1 p1.5/ad5/int1 p0.5/int0 p1.6/int1 p1.7/int1 figure 18-2. S3P9664 pin assignments (24-pin package) table 18-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. (24 dip) i/o function p1.0 sdat 23 i/o serial data pin (output when reading, input when writing) input and push-pull output port can be assigned p1.1 sclk 22 i/o serial clock pin (input only pin) test v pp (test) 5 i 0v : otp write and test mode 5v : operating mode reset reset 8 i chip initialization and eprom cell writing power supply pin (indicates otp mode entering) when writing 12.5v is applied and when reading. v dd /v ss v dd /v ss 24/1 i logic power supply pin. table 18-2. comparison of S3P9664 and s3c9664 features characteristic S3P9664 s3c9664 program memory 4 k byte eprom 4 k byte mask rom operating voltage (v dd ) 4.0 v to 5.25 v 4.0 v to 5.25 v otp programming mode v dd = 5 v, v pp ( reset ) =12.5v pin configuration 20 sop/20 dip/24 sop/24 sdip 20 sop/20 dip/24 sop/24sdip eprom programmability user program 1 time programmed at the factory
s3c9664/p9664 (p reliminary s pec ) development tools 19- 1 19 development tools overview samsung provides a powerf u l and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7, s3c9, s3c8 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, a s sembler, and a program for setting options. shine samsung host interface for i n -circuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, hig hlighted, added, or removed compl etely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm86 the sasm86 is an relocatable assembler for samsung's s3c9 -series microcontrollers. the sasm86 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm86 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code(.obj file) by hex2rom, the value 'ff' is filled into the unused rom area up to the maximum rom size of the targe t device automatically.
development tools s 3c9664/p9664 (p reliminary s pec ) 19- 2 target boards target boards are available for all s3c9 -series microcontrollers. all required target system cables and adapters are included with the device-specific target board. otp s one times programmable microcontrollers ( otps) are under development for s3c9664/p9664 microcontroller. bus smds2+ rs-232c pod probe adapter prom/otp writer unit ram break/display unit trace/timer unit sam8 base unit power supply unit ibm-pc at or compatible tb9664 target board eva chip target application system figure 19-1 . smds product configuration (smds2+)
s3c9664/p9664 (p reliminary s pec ) development tools 19- 3 tb9664 target board the tb9664 target board is used for the s3c9664/p9664 microcontroller s . it is supported by the smds2+ development system. tb9664 sm1330a gnd v cc + idle + stop j101 20-pin socket 20 1 10 11 100-pin connector 25 1 reset to user_v cc off on u2 external triggers ch1 ch2 sw1 smds2 smds2+ 144 qfp s3e9600x eva chip 1 36 figure 19-2 . tb9664 target board configuration
development tools s 3c9664/p9664 (p reliminary s pec ) 19- 4 table 19-1. power selection settings for tb9664 'to user_vcc' settings operating mode comments to user_v cc off on target system smds2/smds2+ tb9664 v cc v ss v cc smds2 /smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_v cc off on target system smds2+ tb9664 external v cc v ss v cc smds2 /smds2+ supplies v cc only to the target board (evaluation chip). the target system must have a power supply of its own . smds2+ selection (sam8) in order to write data into program memory available in smds2+, the target board should be selected for smds2+ through a switch as follows. otherwise, the program memory writing function is not available. table 19-2 . the smds2+ tool selection setting 'sw1' setting operating mode smds2 smds2+ target board smds2+ r/w* r/w*
s3c9664/p9664 (p reliminary s pec ) development tools 19- 5 table 19-3 . using single header pins as the input path for external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) for the smds2+ breakpoint and trace functions. v ss x out x in test p0.0/int0/t0 (cap/pwm) p0.1/int0 reset p0.2/int0 p0.3/int0 p0.4/int0 (note) p0.6/int0 (note) p0.7/int0 v dd d-/p2.0/int2 d+/p2.1/int2 p1.0/ad0/int1 p1.1/ad1/int1 p1.2/ad2/int1 p1.3/ad3/int1 p1.4/ad4/int1 p1.5/ad5/int1 p0.5/int0 p1.6/int1 (note) p1.7/int1 (note) 24-pin socket 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 note: 20 and 24 sop/(s)dip figure 19-3 . 24 -pin socket for tb9664
development tools s 3c9664/p9664 (p reliminary s pec ) 19- 6 target board target system part name: as20p order code: sm6304 20-pin sop/dip socket j101 1 10 20 11 1 20 10 11 figure 19-4 . tb9664 adapter cable for 20 - sop/di p package target board target system part name: ap24sb-a order code: sm6531 24-pin sop/sdip socket j101 1 12 24 13 1 24 12 13 figure 19-5 . tb9664 adapter cable for 24 - sop/sdi p package

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